Abstract: A stack of semiconductor chips includes a substrate or an interposer board comprising conductor structures for electrical connection of the stack and a first chip. The first chip includes an active side with peripherally arranged bonding pads and is mounted face-up on the substrate or the interposer board. The stack beyond includes at least a further chip with peripherally arranged bonding pads on its active side. The back side and at least two chip edges of the further chip are embedded by a mold cap providing a protuberance on the back side of the chip. The protuberance forms a planar surface extending substantially parallel and with a distance to the back side of the chip. The further chip is attached face-up to the active side of the first chip by an adhesive applied between the protuberance and the first chip so that the protuberance is inserted between both chips to provide a gap there. The protuberance has at least one linear dimension that is smaller than a linear dimension of the subjacent chip.

Abstract: A stack of semiconductor chips includes a substrate or an interposer board comprising conductor structures for electrical connection of the stack and a first chip. The first chip includes an active side with peripherally arranged bonding pads and is mounted face-up on the substrate or the interposer board. The stack beyond includes at least a further chip with peripherally arranged bonding pads on its active side. The back side and at least two chip edges of the further chip are embedded by a mold cap providing a protuberance on the back side of the chip. The protuberance forms a planar surface extending substantially parallel and with a distance to the back side of the chip. The further chip is attached face-up to the active side of the first chip by an adhesive applied between the protuberance and the first chip so that the protuberance is inserted between both chips to provide a gap there. The protuberance has at least one linear dimension that is smaller than a linear dimension of the subjacent chip.

Abstract: The present invention generally relates to a method for fabricating a stackable packaged device and a method for producing a packaged device stack utilizing stackable packaged devices. The present invention further refers to a stackable packaged device and a packaged device stack.

Abstract: A method is provided for the solder-stop structuring of elevations on wafers, such as 3D contact structures in the form of resilient or compliant contact bumps, which are connected electrically via a metallization layer to a bonding pad on the wafer, the metallization layer extending over the 3D structure and consisting of a Cu/Ni layer which is covered with a Au layer. The present invention provides a method for the solder-stop structuring of elevations on wafers which can be implemented simply and reliably to produce a reliable solder stop and good flank protection of the 3D structure. According to the invention, a resist is deposited on the tip of a 3D structure and a solder stop layer is then deposited over the metallization, including the resist. The resist on the tip of the 3D structure, including the solder stop layer covering the resist, is subsequently removed so that the Au layer on the tip of the 3D structure is exposed.

Abstract: A method is provided for the solder-stop structuring of elevations on wafers, such as 3D contact structures in the form of resilient or compliant contact bumps, which are connected electrically via a metallization layer to a bonding pad on the wafer, the metallization layer extending over the 3D structure and consisting of a Cu/Ni layer which is covered with a Au layer. The present invention provides a method for the solder-stop structuring of elevations on wafers which can be implemented simply and reliably to produce a reliable solder stop and good flank protection of the 3D structure. According to the invention, a resist is deposited on the tip of a 3D structure and a solder stop layer is then deposited over the metallization, including the resist. The resist on the tip of the 3D structure, including the solder stop layer covering the resist, is subsequently removed so that the Au layer on the tip of the 3D structure is exposed.