Abstract: An improved method and apparatus for performing single-cycle operations (such as for example Maximum a Posteriori, i.e. MAP decode) in digital processors is disclosed. In one exemplary configuration, a processor is fitted with a specialized instruction and extension Arithmetic Logic Unit (ALU) to efficiently perform the forward and reverse transition trellis metric updates as well as the Log Likelihood ratio calculation in order to accelerate the decoding of Turbo-encoded data sequences. The processor executes software comprising the single operand instruction to perform Turbo decoding with the efficiency comparable to a dedicated hardware implementation. The programmable apparatus can be readily reprogrammed to accommodate evolving standards.

Abstract: A method and apparatus are disclosed for decoding according to a Log-MAP algorithm, a bit sequence encoded by a convolutional encoder and received through a noisy channel. A digital signal processor (DSP) for performing the decoding is provided with an extended core possessing a transition metric calculation unit (153) for calculating transition metric values of the encoder trellis for output to a memory store (101,102) of the DSP, and for output to a unit (154) for performing a Log-MAP add-compare-select operation. The Log-MAP add-compare-select unit (154) calculates updated path metric values of the encoder trellis for storage in a memory store (101,102) of the DSP, and for input to a Log-Likelihood Ratio calculating unit (155). The Log-Likelihood Ratio calculating unit (155) are each controlled by the program control unit (104) of the DSP, and communicate with the data memories (101, 102) of the DSP, via data lines (150, 151, 152).

Abstract: An improved method and apparatus for performing single-cycle operations (such as for example Maximum a Posteriori, i.e. MAP decode) in digital processors is disclosed. In one exemplary configuration, a processor is fitted with a specialized instruction and extension Arithmetic Logic Unit (ALU) to efficiently perform the forward and reverse transition trellis metric updates as well as the Log Likelihood ratio calculation in order to accelerate the decoding of Turbo-encoded data sequences. The processor executes software comprising the single operand instruction to perform Turbo decoding with the efficiency comparable to a dedicated hardware implementation. The programmable apparatus can be readily reprogrammed to accommodate evolving standards.

Abstract: An improved method and apparatus for performing single-cycle operations (such as for example Maximum a Posteriori, i.e. MAP decode) in digital processors is disclosed. In one exemplary configuration, a processor is fitted with a specialized instruction and extension Arithmetic Logic Unit (ALU) to efficiently perform the forward and reverse transition trellis metric updates as well as the Log Likelihood ratio calculation in order to accelerate the decoding of Turbo-encoded data sequences. The processor executes software comprising the single operand instruction to perform Turbo decoding with the efficiency comparable to a dedicated hardware implementation. The programmable apparatus can be readily reprogrammed to accommodate evolving standards.

Abstract: A method and apparatus are disclosed for decoding according to a Log-MAP algorithm, a bit sequence encoded by a convolutional encoder and received through a noisy channel. A digital signal processor (DSP) for performing the decoding is provided with an extended core possessing a transition metric calculation unit (153) for calculating transition metric values of the encoder trellis for output to a memory store (101,102) of the DSP, and for output to a unit (154) for performing a Log-MAP add-compare-select operation. The Log-MAP add-compare-select unit (154) calculates updated path metric values of the encoder trellis for storage in a memory store (101,102) of the DSP, and for input to a Log-Likelihood Ratio calculating unit (155). The Log-Likelihood Ratio calculating unit (155) calculates the Log-Likelihood Ratio of a given data bit to be decoded.