Abstract: A process for making silicon on insulator wafer by bond and etch back—BESOI. A boron etch stop is formed by BF2+ ion implantation followed by solid phase epitaxy—SPE. Fluorine getters metals for OISF immunity of the final wafer. SPE activates boron above solubility limit thus facilitates high etch selectivity. Future cap silicon film is epitaxially grown over the boron etch stop at temperature that limits boron diffusion and boron deactivation. High temperature hydrogen bake step in epitaxy is replaced with Siconi of similar low temperature process. Buried oxide is thermally grown from portion of cap silicon layer at temperature limiting Boron diffusion and deactivation. Thus, SOI wafer design is the same as in layer transfer process—bonding interface is at the bottom interface of BOX; properties of final SOI wafer are equal to SOI made by layer transfer process—including cap silicon layer thickness variation, and OISF defect count.

Abstract: A process for making silicon on insulator wafer by bond and etch back—BESOI. Fluorine ion implantation is performed after bonding and after removal of etch stop layers. The ion energy is chosen to have a peak of ion distribution near the wafer bonding interface. The ion dose is chosen to exceed silicon amorphization threshold at maximum ion distribution. The ion dose is chosen low enough to keep silicon surface crystalline. Solid phase epitaxy SPE is performed after the implant. Finalizing of wafer bonding is performed after the SPE by anneal at 800 C. SPE is performed by anneal where temperature is slow ramped up from 450 to 600 C. In further chipmaking process, defect generation as oxidation induced stacking faults—OISFs—during oxidation step is prevented. OISF are not generated even in metal contaminated wafers. As process does not includes high temperature anneal, RF SOI devices—like front chips of smartphones—made on these wafers have advanced RF performance.

Abstract: A process for making silicon on insulator wafer by bond and etch back—BESOI. Fluorine ion implantation is performed after bonding and after removal of etch stop layers. The ion energy is chosen to have a peak of ion distribution near the wafer bonding interface. The ion dose is chosen to exceed silicon amorphization threshold at maximum ion distribution. The ion dose is chosen low enough to keep silicon surface crystalline. Solid phase epitaxy SPE is performed after the implant. Finalizing of wafer bonding is performed after the SPE by anneal at 800 C. SPE is performed by anneal where temperature is slow ramped up from 450 to 600 C. In further chipmaking process, defect generation as oxidation induced stacking faults—OISFs—during oxidation step is prevented. OISF are not generated even in metal contaminated wafers. As process does not includes high temperature anneal, RF SOI devices—like front chips of smartphones—made on these wafers have advanced RF performance.

Abstract: A process for preparing a surface of an optical article to improve light reflection and light transmission properties while conserving mechanical properties as durability and scratch resistance of the surface. A blank film is deposited on a base article. The film is post processed to convert a flat surface into near close packed array of near hemispherical protuberances. The conversion done in 2 steps. First the film is scratched to honeycomb pattern. Second the article is annealed. The anneal causes sequential transformation of flat film into the array. The transformation starts from scratch lines and go to a center of each honeycomb island cell. It is driven by dewetting phenomena. Characteristic size of the protuberances is controlled by initial film thickness. For low reflectivity of visible light, the initial blanket film is near 150 nm thick.

Abstract: A process for preparing a surface of an optical article to improve light reflection and light transmission properties while conserving mechanical properties as durability and scratch resistance of the surface. A blank film is deposited on a base article. The film is post processed to convert a flat surface into near close packed array of near hemispherical protuberances. The conversion done in 2 steps. First the film is scratched to honeycomb pattern. Second the article is annealed. The anneal causes sequential transformation of flat film into the array. The transformation starts from scratch lines and go to a center of each honeycomb island cell. It is driven by dewetting phenomena. Characteristic size of the protuberances is controlled by initial film thickness. For low reflectivity of visible light, the initial blanket film is near 150 nm thick.

Abstract: Process for forming a fragile layer inside of a single crystalline substrate near one of the substrate surfaces. The fragile layer is created by collecting hydrogen in high concentration at a desired depth. The hydrogen layer is collected on a seed layer. The seed layer is formed by ion implantation of non-doping species and annealing. The implantation introduces defects that are capable to trap hydrogen, and annealing confines the seed layer making it flat and thin. Then protium hydrogen ions are implanted at elevated temperature. The protium implantation depth is bigger than the depth of the seed layer. The implanted protium moves to the seed layer and trap there. The process is useful for making silicon-on-insulator (SOI) wafers. SOI with an ultrathin superficial silicon layer of high quality can be obtained. Hydrogen can be implanted at high dose rate, and thus the SOI wafers can be manufactured with high throughput and low cost.

Abstract: A process for manufacturing a silicon-on-insulator wafer from a silicon wafer assembly. The assembly is made of two wafers. One of the wafers contains a fragile layer. The fragile layer is a layer containing a high amount of hydrogen. An amount of energy from an energy source is applied to the assembly to separate the assembly along the fragile layer thus forming a silicon-on-insulator wafer and a leftover wafer. The energy source is selected from the group consisting of: ultrasound, infrared, hydrostatic pressure, hydrodynamic pressure, or mechanical energy. The amount of energy is chosen to be sufficient to transform the fragile layer into a quasi-continuous gaseous layer. Under separation the hydrogen-enriched layer transforms into layer consisting of hydrogen platelets and hydrogen microbubbles.

Abstract: A process for manufacturing a silicon-on-insulator substrate and semiconductor devices on said substrate from thermally oxidized silicon wafer so that processing temperatures are limited to 900° C. is disclosed. The substrate is fabricated using H2 split process. Processing temperatures are limited to temperature of initiating of out-diffusion of oxygen from silicon dioxide into silicon. The limit prevents deterioration of buried oxide, and the oxide has low hole trap density that is equal to the trap density of an initial thermal silicon dioxide. Processing temperatures after implantation for H2 split process are limited to temperature of stability of dislocation microloops induced by the implantation at its damage peak. Resulting SOI structure have a gettering layer made from the microloops. The getter prevents yield drop caused by heavy metal contamination during the fabrication. Finished SOI devices have improved gate oxide integrity.

Abstract: A method for forming ICs comprising a highly-resistive or semi-insulating semiconductor substrate having a thin, low resistance active semiconductor layer thereon. In accordance with one embodiment of the method, the entire semiconductor substrate with at least partially prefabricated semiconductor devices disposed thereon is subjected to irradiation sufficient to impart high resistance throughout the substrate and active semiconductor layer. A thin, low resistance, active semiconductor layer is then generated on the substrate body by localized annealing. The (partially) prefabricated semiconductor devices are restored to operability by virtue of the annealing step as defects in the top insulating layers and properties of thin layers underneath the insulator-semiconductor interfaces are “healed.” The annealing step does not, however, heal the defects in the bulk substrate so that it remains semi-insulating.

Abstract: Process for lift-off of a thin layer from a crystalline substrate, preferably the layer from a silicon wafer to further form a silicon-on-insulator (SOI) sandwich structure, wherein a separative interlayer comprises a thin quasi-continuous gaseous layer and said interlayer is obtained by gettering a monatomic hydrogen into a preformed buried defect-rich layer preferably obtained by implantation. The monatomic hydrogen is preferably inserted into the substrate by electrolytic means.