Patents by Inventor Alexander Z. Zelikovsky

Alexander Z. Zelikovsky has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Floorplan evaluation, global routing, and buffer insertion for integrated circuits
    Patent number: 7062743
    Abstract: A method and system for evaluating a floorplan and for defining a global buffered routing for an integrated circuit including constructing a graphical representation of the integrated circuit floorplan, including wire capacity and buffer capacity; formulating an integer linear program from said graphical representation; finding a solution to said integer linear program.
    Type: Grant
    Filed: September 24, 2003
    Date of Patent: June 13, 2006
    Assignee: The Regents of the University of California
    Inventors: Andrew B. Kahng, Christoph Albrecht, Ion I. Mandoiu, Alexander Z. Zelikovsky
  • Floorplan evaluation, global routing, and buffer insertion for integrated circuits
    Publication number: 20040117753
    Abstract: A method and system for evaluating a floorplan and for defining a global buffered routing for an integrated circuit including constructing a graphical representation of the integrated circuit floorplan, including wire capacity and buffer capacity; formulating an integer linear program from said graphical representation; finding a solution to said integer linear program.
    Type: Application
    Filed: September 24, 2003
    Publication date: June 17, 2004
    Applicant: The Regents of the University of California
    Inventors: Andrew B. Kahng, Christoph Albrecht, Ion I. Mandoiu, Alexander Z. Zelikovsky