Abstract: The present disclosure relates to authenticity and data security for bus-based communication networks in a vehicle. The present disclosure teaches a protocol frame, a sender on data link layer, and a receiver on data link layer providing such authenticity and data security as well as a communication network in a vehicle employing the protocol frame, the sender and the receiver according to the present disclosure.

Abstract: A method for cryptographic data processing by means of a circuit comprises using a first circuit section to perform a first cryptographic operation in order to obtain first cryptographic data. The method further includes transmitting the first cryptographic data to a second circuit section via a transmission area of the circuit that physically separates the second circuit section from the first circuit section and whose resistance to attacks is at most as high as the resistance of the first circuit section. The method includes using the second circuit section to perform a second cryptographic operation using the first cryptographic data in order to obtain second cryptographic data.

Abstract: A data message authentication system in a vehicle communication network includes a sequence generator configured to generate a sequence representative of an intra-message pattern; a parsing processor configured to receive a data message, receive the sequence from the sequence generator, select a subset of data segments from the data message based on the intra-message pattern, and output the selected subset of data segments; and a tag generator configured to receive the selected subset of data segments from the parsing processor and generate an authentication code based on the selected subset of data segments, where the authentication code corresponds to the data message.

Abstract: A redundancy system includes a first computational device and a second computational device each configured to receive at least one input and to generate a first output and a second output, respectively, based on the at least one input; a random sequence generator configured to generate a random bit sequence; a random delay selector configured to determine a random delay based on the random bit sequence; a first random delay circuit configured to delay outputting the at least one input to the first computational device based on the random delay; a second random delay circuit configured to delay outputting the second output based on the random delay; and a fault detection circuit configured to receive the first output and the delayed second output, and to generate a comparison result based on comparing the first input to the delayed second output.

Abstract: The present disclosure relates to a security device, a system, and a method for securing a control apparatus. The security device includes a data security unit which is configured to secure data, data communication and information, and includes a first security component inside the data security unit to operate in a first operating mode, and at least one first monitoring unit to operate in a high-availability mode which, said first monitoring unit being configured to detect a fault present in the first security component. The high-availability mode is different from the first operating mode. The security device further includes a second security component which is configured to operate in the high-availability mode and to output a first response signal if a fault is detected by the first monitoring, where the high-availability mode is available independently from the first operating mode.

Abstract: A security hardware device is configured to secure a control apparatus. The security hardware device includes a data security domain; a functional safety domain; a data security processor provided in the data security domain and is configured to secure data from unauthorized access or manipulation; a functional safety processor provided in the functional safety domain and is configured to detect functional errors and generate respective safety alerts in response to detecting the functional errors; and a monitoring processor configured to analyze the respective safety alerts provided by the functional safety processor for at least one pattern of safety alerts indicative of a security attack and generate a response signal in response to the respective safety alerts having at least one of the at least one pattern of safety alerts.

Abstract: An authentication system includes a microcontroller having a unique identifier (ID) and a first key pair including a microcontroller secret key and a microcontroller public key. The microcontroller is configured to store the unique ID, the first key pair, a digital signature of the unique ID, the digital signature being generated using an external secret key of a second key pair, and a digital certificate of the microcontroller public key that is signed by the external secret key of the second key pair. The second key pair includes the external secret key and an external public key. The authentication system further includes a controller configured to perform a first authenticity validation check on the unique ID using the external public key and perform a second authenticity validation check on the microcontroller public key using the external public key.

Abstract: A sender device may include a transmitter and one or more processors. The one or more processors may be configured to transmit, to one or more receiver devices, a frame via a communication bus. The one or more processors may be configured to detect a replicated frame on the communication bus, and identify an attack event based on detecting the replicated frame. The one or more processors may be configured to determine a sequence of interframe transmit times based on identifying the attack event, wherein the sequence of interframe transmit times is determined based on a shared secret associated with the one or more receiver devices. The one or more processors may be configured to transmit a series of alert frames according to the sequence of interframe transmit times to permit the one or more receiver devices to be notified of the attack event.

Abstract: The present disclosure relates to authenticity and data security for bus-based communication networks in a vehicle. The present disclosure teaches a protocol frame, a sender on data link layer, and a receiver on data link layer providing such authenticity and data security as well as a communication network in a vehicle employing the protocol frame, the sender and the receiver according to the present disclosure.

Abstract: A bus-based communication system, may include a communication bus connecting a plurality of nodes. A first node, of the plurality of nodes, may receive a first message on the communication bus, the first message having been broadcast on the communication bus by a second node of the plurality of nodes. The first message may include a modular exponentiation associated with a private key of the second node. The first node may compute a shared secret key, associated with the plurality of nodes, based at least in part on the modular exponentiation and a private key of the first node.

Abstract: A transmitter device of a bus-based communication system may add one or more padding bits, associated with providing traffic flow confidentiality for communication of a payload on a communication bus, either to the payload on a transport layer, or to one or more first frames on a data link layer. The one or more first frames may include a transport layer payload associated with the payload. The transmitter device may transmit one or more second frames, including a data link layer payload associated with the one or more first frames, on the communication bus. A receiver device of the bus-based communication system may receive the one or more second frames on the communication bus. The receiver device may process the one or more padding bits from either the one or more first frames on the data link layer, or from the payload on the transport layer.

Abstract: A hybrid device includes a plurality of diverse subsystems, including a first and a second subsystem. The first subsystem includes at least one first secured storage device configured to store a first software and a first CPU configured to boot and execute the first software. The second subsystem includes at least one second secured storage device configured to store a second software and a second CPU configured to boot and execute the second software. The first CPU is configured to generate the first hash of the first software and transmit the generated first hash of the first software to the second subsystem. The second CPU is configured to perform a first authenticity validation check on the first software using the received first hash of the first software, and generate an error signal on a condition that the first authenticity validation check on the first software fails.

Abstract: The disclosure creates a method for generating a proof-of-work. In the method, a data block is associated with a nonce. Then, the data block associated with the nonce is encrypted into a tag using a secret key. In a further step it is checked whether the tag meets a predetermined criterion. If the tag does not meet the predetermined criterion, the nonce is varied and the association and encryption are repeated until the check shows that the tag meets the criterion. In addition, the disclosure relates to the implementation of the proof-of-work during the process of authentication, encryption, transmission and reception of a message. In addition, the disclosure relates to a computer program and a device for carrying out the method.

Abstract: A data cryptographic device may include a pre-tweak generator to generate pre-tweak values, a pre-tweak value cache memory to store one or more pre-tweak values generated by the pre-tweak generator, and a pre-tweak value selector to check whether a pre-tweak value for an input memory address is stored in the pre-tweak value cache memory. The data cryptographic device may further include a tweak generator to generate a tweak value based on the selected pre-tweak value, and a block cipher to perform at least one block cipher algorithm to at least one of encrypt data, encrypt and authenticate data, decrypt encrypted data, decrypt and verify encrypted and authenticated data, using a cryptographic key and the generated tweak value.

Abstract: A device is suggested including a cryptographic module, wherein the device is operable in a secure mode and in a non-secure mode, wherein the cryptographic module is configured in the secure mode by storing a secret key and a seed value in the cryptographic module, and wherein the device is operable in the non-secure mode to generate a signature based on input data utilizing the secret key and the seed value. Also, a method for operating such device is provided.

Abstract: A device is suggested for processing input data including a hardware accelerator generating a first hash value based on a first portion of the input data and a second hash value based on a second portion of the input data, wherein the first hash value is generated based on a first configuration of the hardware accelerator and wherein the second hash value is generated based on a second configuration of the hardware accelerator. Also, a method for operating such device is provided.

Abstract: A method for processing data in a plurality of processing acts includes: configuring a plurality of processing circuits in a first configuration, in such a way that both a first and a second of the plurality of processing circuits execute a first of the plurality of processing acts; and configuring the plurality of processing circuits in a second configuration, in such a way that the first processing circuit executes a second processing act and the second processing circuit executes a third processing act, which is different than the second processing act. An apparatus is designed for carrying out the method.

Abstract: A Cryptographic Unit (CU) of a microcontroller, the CU including a first accelerator configured to generate first encrypted output data based on input data; and a second accelerator which is configured to be diversely implemented with respect to the first accelerator, and is configured to generate second encrypted output data based on the input data; and a comparator configured to compare a first comparator data obtained from the generation of the first encrypted output data with a second comparator data obtained from the generation of the second encrypted output data, and if the comparison indicates that the first and second comparator data differ, output an event signal pertaining to an event in a safety domain or a security domain.

Abstract: A sender device may include a transmitter and one or more processors. The one or more processors may be configured to transmit, to one or more receiver devices, a frame via a communication bus. The one or more processors may be configured to detect a replicated frame on the communication bus, and identify an attack event based on detecting the replicated frame. The one or more processors may be configured to determine a sequence of interframe transmit times based on identifying the attack event, wherein the sequence of interframe transmit times is determined based on a shared secret associated with the one or more receiver devices. The one or more processors may be configured to transmit a series of alert frames according to the sequence of interframe transmit times to permit the one or more receiver devices to be notified of the attack event.

Abstract: An authentication system includes a microcontroller having a unique identifier (ID) and a first key pair including a microcontroller secret key and a microcontroller public key. The microcontroller is configured to store the unique ID, the first key pair, a digital signature of the unique ID, the digital signature being generated using an external secret key of a second key pair, and a digital certificate of the microcontroller public key that is signed by the external secret key of the second key pair. The second key pair includes the external secret key and an external public key. The authentication system further includes a controller configured to perform a first authenticity validation check on the unique ID using the external public key and perform a second authenticity validation check on the microcontroller public key using the external public key.