Patents by Inventor Alexandra Bauche
Alexandra Bauche has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10884628Abstract: Improving performance of a read in a memory system. Various methods include: reading data from a word line in a memory block, where during the read, associated parameters are generated that include: a value indicative of a throughput time, and a value indicative of a bit error rate (BER); retrieving the value indicative of the throughput time and the value indicative of the BER; and performing a read improvement process if the value indicative of the throughput time is above a threshold value. The method also includes performing the read improvement process by: flagging the memory block if the value indicative of the BER is at or below and expected BER; and performing cleanup operations if the value indicative of the BER is higher than the expected BER.Type: GrantFiled: December 20, 2018Date of Patent: January 5, 2021Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Niles Yang, Phil Reusswig, Alexandra Bauche
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Patent number: 10732856Abstract: An exemplary method to rank blocks of a non-volatile memory device includes: for each of a plurality of blocks of a memory device, determining a respective erase health metric (EHM) for each of the blocks by combining an erase difficulty metric and an age metric, including: calculating the erase difficulty metric for a respective block based on erase performance metrics obtained during erase phases of an erase operation performed on the respective block, and determining the age metric for the respective block based on a total number of erase operations performed on the respective block during its lifespan. After determining the respective EHM for each of the blocks, the method includes ranking blocks in accordance with the determined respective EHMs, and selecting a block of the plurality of blocks in accordance with the rankings, and writing data to the selected block.Type: GrantFiled: October 4, 2016Date of Patent: August 4, 2020Assignee: SanDisk Technologies LLCInventors: Nian Niles Yang, Alexandra Bauche
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Publication number: 20200201546Abstract: Improving performance of a read in a memory system. Various methods include: reading data from a word line in a memory block, where during the read, associated parameters are generated that include: a value indicative of a throughput time, and a value indicative of a bit error rate (BER); retrieving the value indicative of the throughput time and the value indicative of the BER; and performing a read improvement process if the value indicative of the throughput time is above a threshold value. The method also includes performing the read improvement process by: flagging the memory block if the value indicative of the BER is at or below and expected BER; and performing cleanup operations if the value indicative of the BER is higher than the expected BER.Type: ApplicationFiled: December 20, 2018Publication date: June 25, 2020Inventors: Niles Yang, Phil Reusswig, Alexandra Bauche
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Patent number: 9965199Abstract: A memory system or flash card may include a dynamic system-level process for the management of blocks in the different memory pools. There may be spare blocks available to the pools that are over provisioned to the pool which increases the efficiency of data compaction and helps reduce the average hot count for that pool and compensate for the grown defects. The block wear and grown defects in each memory pool may be tracked so that remaining spare blocks can be re-allocated.Type: GrantFiled: August 22, 2013Date of Patent: May 8, 2018Assignee: SanDisk Technologies LLCInventors: Gautham Reddy, Nian Niles Yang, Alexandra Bauche, Nagdi Tafish, Michael Zhu
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Patent number: 9927987Abstract: The various implementations described herein include systems, methods and/or devices used to enable multi-phase erasure in a storage device. The method includes performing an erase operation on a portion of one or more non-volatile memory devices, by performing a sequence of erase phase operations until an erase operation stop condition is satisfied. Each erase phase operation includes: performing an erase phase on the portion of the non-volatile memory devices using an erase voltage, and determining an erase phase statistic for the erase phase. For each erase phase operation in the sequence of erase phase operations, other than a first erase phase operation, the erase voltage used when performing the erase phase operation is equal to the erase voltage used when performing a prior erase phase operation in the sequence of erase phase operations plus an erase voltage increment based on the erase phase statistic for the prior erase phase operation.Type: GrantFiled: October 30, 2015Date of Patent: March 27, 2018Assignee: SANDISK TECHNOLOGIES LLCInventors: Nian Niles Yang, Alexandra Bauche
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Publication number: 20170255399Abstract: An exemplary method to rank blocks of a non-volatile memory device includes: for each of a plurality of blocks of a memory device, determining a respective erase health metric (EHM) for each of the blocks by combining an erase difficulty metric and an age metric, including: calculating the erase difficulty metric for a respective block based on erase performance metrics obtained during erase phases of an erase operation performed on the respective block, and determining the age metric for the respective block based on a total number of erase operations performed on the respective block during its lifespan. After determining the respective EHM for each of the blocks, the method includes ranking blocks in accordance with the determined respective EHMs, and selecting a block of the plurality of blocks in accordance with the rankings, and writing data to the selected block.Type: ApplicationFiled: October 4, 2016Publication date: September 7, 2017Inventors: Nian Niles Yang, Alexandra Bauche
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Publication number: 20170060445Abstract: The various implementations described herein include systems, methods and/or devices used to enable multi-phase erasure in a storage device. The method includes performing an erase operation on a portion of one or more non-volatile memory devices, by performing a sequence of erase phase operations until an erase operation stop condition is satisfied. Each erase phase operation includes: performing an erase phase on the portion of the non-volatile memory devices using an erase voltage, and determining an erase phase statistic for the erase phase. For each erase phase operation in the sequence of erase phase operations, other than a first erase phase operation, the erase voltage used when performing the erase phase operation is equal to the erase voltage used when performing a prior erase phase operation in the sequence of erase phase operations plus an erase voltage increment based on the erase phase statistic for the prior erase phase operation.Type: ApplicationFiled: October 30, 2015Publication date: March 2, 2017Inventors: Nian Niles Yang, Alexandra Bauche
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Patent number: 9535614Abstract: A memory system or flash card may include memory maintenance scheduling that improves the endurance of memory. Certain parameters, such as temperature, are measured and used for scheduling maintenance. For example, memory maintenance may be performed or postponed depending on the ambient temperature of the card. The memory maintenance operations may be ranked or classified (e.g. in a memory maintenance queue based on priority) to correspond with threshold values of the parameters for a more efficient scheduling of memory maintenance. For example, at a low temperature threshold, only high priority maintenance operations are performed, while at a higher temperature threshold, any priority maintenance operation is performed.Type: GrantFiled: November 21, 2013Date of Patent: January 3, 2017Assignee: SanDisk Technologies LLCInventors: Gautham Reddy, Nian Niles Yang, Alexandra Bauche
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Patent number: 9478315Abstract: A memory system or flash memory device may include identify a bit error rate (BER) mapping for the memory. The BER mapping may be used for identifying erroneous bits, managing them, and using them for the system maintenance and system recovery. A complete BER map may be stored in main memory while a cached version of the BER map may be stored in random access memory (RAM). The cached version may identify only the top and bottom bits rather than the complete map. The cached BER map may be updated based on future reads and future programming may rely on the cached BER map for selecting blocks to program.Type: GrantFiled: June 3, 2014Date of Patent: October 25, 2016Assignee: SanDisk Technologies LLCInventors: Nian Niles Yang, Jianmin Huang, Alexandra Bauche
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Patent number: 9411669Abstract: Data stored in a nonvolatile memory is selectively sampled based on write-erase cycle counts of blocks. Blocks with the lowest write-erase cycle counts are sampled to determine an error rate which is compared with a limit. If the error rate exceeds the limit then the sample is expanded to include blocks with the next lowest write-erase cycle counts.Type: GrantFiled: September 11, 2014Date of Patent: August 9, 2016Assignee: SanDisk Technologies LLCInventors: Gautham Kumar Reddy, Niles Yang, Alexandra Bauche
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Publication number: 20160078960Abstract: Devices and methods implemented therein are disclosed for storing data in memory pages of a non-volatile memory of the storage device. The device comprises a non-volatile memory, a reading circuit, a programming circuit and a read disturb detector. The non-volatile memory has an erased memory page comprising a plurality of multi-layer cells (MLCs). The reading circuit is configured to read a respective electric charge stored in each of the plurality of MLCs. The programming circuit is configured to store data in the plurality of MLCs at either one of a first storage density or a second storage density. The read disturb detector is configured to determine whether the erased memory page is read disturbed and if the erased memory page is read disturbed, cause the programming circuit to store data into the MLCs at the second storage density that is less than the first storage density.Type: ApplicationFiled: September 12, 2014Publication date: March 17, 2016Inventors: Nian Yang, Jianmin Huang, Ting Luo, Alexandra Bauche, Nagdi Tafish
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Publication number: 20160077903Abstract: Data stored in a nonvolatile memory is selectively sampled based on write-erase cycle counts of blocks. Blocks with the lowest write-erase cycle counts are sampled to determine an error rate which is compared with a limit. If the error rate exceeds the limit then the sample is expanded to include blocks with the next lowest write-erase cycle counts.Type: ApplicationFiled: September 11, 2014Publication date: March 17, 2016Inventors: Gautham Kumar Reddy, Niles Yang, Alexandra Bauche
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Patent number: 9245637Abstract: Non-volatile memory and methods of reading non-volatile memory are provided for managing and reducing read related disturb. Techniques are introduced to reduce read disturb using state-dependent read pass voltages for particular word lines during a read operation. Because of their proximity to a selected word line, adjacent word lines can be biased using state-dependent pass voltages while other unselected word lines are biased using a standard or second set of pass voltages. Generally, each state-dependent pass voltage applied to a word line adjacent to the selected word line is larger than the second set of pass voltages applied to other unselected word lines, although this is not required. Other word lines, may also be biased using state-dependent pass voltages. System-level techniques are provided with or independently of state-dependent pass voltages to further reduce and manage read disturb. Techniques may account for data validity and memory write and erase cycles.Type: GrantFiled: September 6, 2013Date of Patent: January 26, 2016Assignee: SanDisk Technologies Inc.Inventors: Nian Niles Yang, Chris Avila, Steven Sprouse, Alexandra Bauche
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Publication number: 20150348649Abstract: A memory system or flash memory device may include identify a bit error rate (BER) mapping for the memory. The BER mapping may be used for identifying erroneous bits, managing them, and using them for the system maintenance and system recovery. A complete BER map may be stored in main memory while a cached version of the BER map may be stored in random access memory (RAM). The cached version may identify only the top and bottom bits rather than the complete map. The cached BER map may be updated based on future reads and future programming may rely on the cached BER map for selecting blocks to program.Type: ApplicationFiled: June 3, 2014Publication date: December 3, 2015Inventors: Nian Niles Yang, Jianmin Huang, Alexandra Bauche
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Patent number: 9070449Abstract: In a flash memory, erase blocks containing shorted or broken word lines may be used, at least in part, to store user data. Such blocks may use different parameters to those used by non-defective blocks, may be subject to different wear leveling, and may store data selected to reduce the number of access operations.Type: GrantFiled: April 26, 2013Date of Patent: June 30, 2015Assignee: SanDisk Technologies Inc.Inventors: Nian Niles Yang, Uday Chandrasekhar, Yichao Huang, Alexandra Bauche, William S. Wu
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Patent number: 9053808Abstract: A method and system have been described for counteracting and correcting for read disturb effects in blocks of flash memory. The method may include the step of a controller of the memory system performing a read scrub scan on only a portion of one targeted word line in a block at desired intervals. The controller may calculate whether a read scrub scan is necessary based on a probabilistic determination that is calculated in response to each received host read command. The controller may then place a block associated with the targeted word line into a refresh queue if a number of errors are detected in the targeted word line that meets or exceeds a predetermined threshold. The block refresh process may include copying the data from the block into a new block during a background operation.Type: GrantFiled: June 21, 2012Date of Patent: June 9, 2015Assignee: SanDisk Technologies Inc.Inventors: Steven T. Sprouse, Alexandra Bauche, Yichao Huang, Jian Chen, Jianmin Huang, Dana Lee
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Publication number: 20150143026Abstract: A memory system or flash card may include memory maintenance scheduling that improves the endurance of memory. Certain parameters, such as temperature, are measured and used for scheduling maintenance. For example, memory maintenance may be performed or postponed depending on the ambient temperature of the card. The memory maintenance operations may be ranked or classified (e.g. in a memory maintenance queue based on priority) to correspond with threshold values of the parameters for a more efficient scheduling of memory maintenance. For example, at a low temperature threshold, only high priority maintenance operations are performed, while at a higher temperature threshold, any priority maintenance operation is performed.Type: ApplicationFiled: November 21, 2013Publication date: May 21, 2015Applicant: SanDisk Technologies Inc.Inventors: Gautham Reddy, Nian Niles Yang, Alexandra Bauche
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Publication number: 20150071008Abstract: Non-volatile memory and methods of reading non-volatile memory are provided for managing and reducing read related disturb. Techniques are introduced to reduce read disturb using state-dependent read pass voltages for particular word lines during a read operation. Because of their proximity to a selected word line, adjacent word lines can be biased using state-dependent pass voltages while other unselected word lines are biased using a standard or second set of pass voltages. Generally, each state-dependent pass voltage applied to a word line adjacent to the selected word line is larger than the second set of pass voltages applied to other unselected word lines, although this is not required. Other word lines, may also be biased using state-dependent pass voltages. System-level techniques are provided with or independently of state-dependent pass voltages to further reduce and manage read disturb. Techniques may account for data validity and memory write and erase cycles.Type: ApplicationFiled: September 6, 2013Publication date: March 12, 2015Applicant: SanDisk Technologies Inc.Inventors: Nian Niles Yang, Chris Avila, Steven Sprouse, Alexandra Bauche
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Publication number: 20150058530Abstract: A memory system or flash card may include a dynamic system-level process for the management of blocks in the different memory pools. There may be spare blocks available to the pools that are over provisioned to the pool which increases the efficiency of data compaction and helps reduce the average hot count for that pool and compensate for the grown defects. The block wear and grown defects in each memory pool may be tracked so that remaining spare blocks can be re-allocated.Type: ApplicationFiled: August 22, 2013Publication date: February 26, 2015Inventors: Gautham Reddy, Nian Niles Yang, Alexandra Bauche, Nagdi Tafish, Michael Zhu
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Publication number: 20140321202Abstract: In a flash memory, erase blocks containing shorted or broken word lines may be used, at least in part, to store user data. Such blocks may use different parameters to those used by non-defective blocks, may be subject to different wear leveling, and may store data selected to reduce the number of access operations.Type: ApplicationFiled: April 26, 2013Publication date: October 30, 2014Applicant: SanDisk Technologies, Inc.Inventors: Nian Niles Yang, Uday Chandrasekhar, Yichao Huang, Alexandra Bauche, William S. Wu