Abstract: A method for fabricating a SiC power semiconductor device includes: providing a SiC power semiconductor die; depositing a metallization layer over the power semiconductor die, the metallization layer including a first metal; arranging the power semiconductor die over a die carrier such that the metallization layer faces the die carrier, the die carrier being at least partially covered by a plating that includes Ni; and diffusion soldering the power semiconductor die to the die carrier such that a first intermetallic compound is formed between the power semiconductor die and the plating, the first intermetallic compound including Ni3Sn4.

Abstract: A semiconductor package includes a power semi conductor chip comprising SiC, a leadframe part including Cu, wherein the power semiconductor chip is arranged on the leadframe part, and a solder joint electrically and mechanically coupling the power semiconductor chip to the leadframe part, wherein the solder joint includes at least one intermetallic phase.

Abstract: A semiconductor package includes a power semiconductor chip comprising SiC, a leadframe part comprising Cu, wherein the power semiconductor chip is arranged on the leadframe part, and a solder joint electrically and mechanically coupling the power semiconductor chip to the leadframe part, wherein the solder joint comprises at least one intermetallic phase.

Abstract: A SiC power semiconductor device includes: a power semiconductor die including SiC and a metallization layer, wherein the metallization layer includes a first metal; a die carrier, wherein the power semiconductor die is arranged over the die carrier such that the metallization layer faces the die carrier, the die carrier being at least partially covered by a plating that includes Ni; and a first intermetallic compound arranged between the power semiconductor die and the plating and including Ni3Sn4.

Abstract: A semiconductor package includes a power semiconductor chip comprising SiC, a leadframe part comprising Cu, wherein the power semiconductor chip is arranged on the leadframe part, and a solder joint electrically and mechanically coupling the power semiconductor chip to the leadframe part, wherein the solder joint comprises at least one intermetallic phase.

Abstract: A power semiconductor transistor includes an electrically conductive contact structure including a plurality of contacts. A first one of the contacts is electrically connected to both a first load terminal and a first zone of a doped semiconductor structure. A second one of the contacts is electrically coupled to one of the first load terminal and a control electrode. The second contact laterally overlaps with both a second zone of the doped semiconductor structure, and a gap is formed between two adjacent field plates. The second zone of the doped semiconductor structure terminates in a section laterally overlapping with the gap.

Abstract: A power semiconductor transistor includes an electrically conductive contact structure including a plurality of contacts. A first one of the contacts is electrically connected to both a first load terminal and a first zone of a doped semiconductor structure. A second one of the contacts is electrically coupled to one of the first load terminal and a control electrode. The second contact laterally overlaps with both a second zone of the doped semiconductor structure, and a gap is formed between two adjacent field plates. The second zone of the doped semiconductor structure terminates in a section laterally overlapping with the gap.