Patents by Inventor Alexandre Ayres

Alexandre Ayres has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11573260
    Abstract: An integrated circuit chip is attached to a support that includes first conductive elements. First conductive pads are located on the integrated circuit chip and are electrically coupled to the first conductive elements by conductive wires. The integrated circuit chip further includes a conductive track. A switch circuit is provided to selectively electrically connect each first conductive pad to the conductive track. To test the conductive wires, a group of first conductive pads are connected by their respective switch circuits to the conductive track and current flow between corresponding first conductive elements is measured.
    Type: Grant
    Filed: December 6, 2021
    Date of Patent: February 7, 2023
    Assignee: STMicroelectronics (Grolles 2) SAS
    Inventors: Alexandre Ayres, Bertrand Borot
  • Publication number: 20220178989
    Abstract: An integrated circuit chip is attached to a support that includes first conductive elements. First conductive pads are located on the integrated circuit chip and are electrically coupled to the first conductive elements by conductive wires. The integrated circuit chip further includes a conductive track. A switch circuit is provided to selectively electrically connect each first conductive pad to the conductive track. To test the conductive wires, a group of first conductive pads are connected by their respective switch circuits to the conductive track and current flow between corresponding first conductive elements is measured.
    Type: Application
    Filed: December 6, 2021
    Publication date: June 9, 2022
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Alexandre AYRES, Bertrand BOROT
  • Patent number: 11251175
    Abstract: A three-dimensional integrated structure is formed by a first substrate with first components oriented in a first direction and a second substrate with second components oriented in a second direction. An interconnection level includes electrically conducting tracks that run in a third direction. One of the second direction and third direction forms a non-right and non-zero angle with the first direction. An electrical link formed by at least one of the electrically conducting tracks electrically connected two points of the first or of the second components.
    Type: Grant
    Filed: September 6, 2019
    Date of Patent: February 15, 2022
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Alexandre Ayres, Bertrand Borot
  • Publication number: 20190393207
    Abstract: A three-dimensional integrated structure is formed by a first substrate with first components oriented in a first direction and a second substrate with second components oriented in a second direction. An interconnection level includes electrically conducting tracks that run in a third direction. One of the second direction and third direction forms a non-right and non-zero angle with the first direction. An electrical link formed by at least one of the electrically conducting tracks electrically connected two points of the first or of the second components.
    Type: Application
    Filed: September 6, 2019
    Publication date: December 26, 2019
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Alexandre AYRES, Bertrand BOROT
  • Patent number: 10446535
    Abstract: A three-dimensional integrated structure is formed by a first substrate with first components oriented in a first direction and a second substrate with second components oriented in a second direction. An interconnection level includes electrically conducting tracks that run in a third direction. One of the second direction and third direction forms a non-right and non-zero angle with the first direction. An electrical link formed by at least one of the electrically conducting tracks electrically connected two points of the first or of the second components.
    Type: Grant
    Filed: April 25, 2016
    Date of Patent: October 15, 2019
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Alexandre Ayres, Bertrand Borot
  • Patent number: 10075694
    Abstract: A semiconductor chip includes a plurality of superposed semiconductor levels. The semiconductor levels include a plurality of elementary circuits coupled to a common input node. Sensing circuits are coupled to elementary elements of different levels. The outputs of the sensing circuits are used to generate a number, which serves as an identification number of the semiconductor chip.
    Type: Grant
    Filed: August 18, 2017
    Date of Patent: September 11, 2018
    Assignee: STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Alexandre Ayres, Bertrand Borot
  • Publication number: 20180192027
    Abstract: A semiconductor chip includes a plurality of superposed semiconductor levels. The semiconductor levels include a plurality of elementary circuits coupled to a common input node. Sensing circuits are coupled to elementary elements of different levels. The outputs of the sensing circuits are used to generate a number, which serves as an identification number of the semiconductor chip.
    Type: Application
    Filed: August 18, 2017
    Publication date: July 5, 2018
    Inventors: Alexandre AYRES, Bertrand BOROT
  • Publication number: 20170179104
    Abstract: A three-dimensional integrated structure is formed by a first substrate with first components oriented in a first direction and a second substrate with second components oriented in a second direction. An interconnection level includes electrically conducting tracks that run in a third direction. One of the second direction and third direction forms a non-right and non-zero angle with the first direction. An electrical link formed by at least one of the electrically conducting tracks electrically connected two points of the first or of the second components.
    Type: Application
    Filed: April 25, 2016
    Publication date: June 22, 2017
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Alexandre Ayres, Bertrand Borot