Patents by Inventor Alexandre Benjamin FONSECA

Alexandre Benjamin FONSECA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and device for auto-calibration of multi-gate circuits
    Patent number: 10164573
    Abstract: A differential-logic logic circuit chained with another differential-logic circuit comprises a first logic cell composed of back-gate transistors, the first cell having a first input for receiving a first input signal and having an output for delivering a first output signal, and a second logic cell complementary to the first cell, composed of back-gate transistors, the second cell having as many inputs as the first cell, each input able to receive an input signal complementary to the respective input signal of the first cell, the second cell having an output for delivering a second output signal complementary to the first output signal of the first cell. The first output signal of the first cell is applied to the back gate of each transistor of the second cell, and the second output signal of the second cell is applied to the back gate of each transistor of the first cell.
    Type: Grant
    Filed: April 8, 2016
    Date of Patent: December 25, 2018
    Assignees: UNIVERSITE DE NICE, COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Gilles Fernand Jacquemod, Emeric De Foucauld, Alexandre Benjamin Fonseca, Yves Leduc, Philippe Bernard Pierre Lorenzini
  • Method and device for auto-calibration of multi-gate circuits
    Publication number: 20160301365
    Abstract: A differential-logic logic circuit chained with another differential-logic circuit comprises a first logic cell composed of back-gate transistors, the first cell having a first input for receiving a first input signal and having an output for delivering a first output signal, and a second logic cell complementary to the first cell, composed of back-gate transistors, the second cell having as many inputs as the first cell, each input able to receive an input signal complementary to the respective input signal of the first cell, the second cell having an output for delivering a second output signal complementary to the first output signal of the first cell. The first output signal of the first cell is applied to the back gate of each transistor of the second cell, and the second output signal of the second cell is applied to the back gate of each transistor of the first cell.
    Type: Application
    Filed: April 8, 2016
    Publication date: October 13, 2016
    Inventors: Gilles Fernand JACQUEMOD, Emeric DE FOUCAULD, Alexandre Benjamin FONSECA, Yves LEDUC, Philippe Bernard Pierre LORENZINI