Abstract: The electronic architecture carries out the management of the functions of a vehicle, the functions being implemented via a set of sensors and actuators, the architecture comprising at least: a central computer; a real-time communication network; a set of interface modules, each module: aggregating signals from at least one of the sensors and sending the signals to the central computer via the communication network; and/or distributing control signals to at least one of the actuators; the central computer driving the actuators according to the signals from the sensors, the control signals for the actuators being sent to the interface modules via the communication network.

Abstract: A circuit comprises a series of calculating blocks that can each implement a group of neurons; a transformation block that is linked to the calculating blocks by a communication means and that can be linked at the input of the circuit to an external data bus, the transformation block transforming the format of the input data and transmitting the data to said calculating blocks by means of K independent communication channels, an input data word being cut up into sub-words such that the sub-words are transmitted over multiple successive communication cycles, one sub-word being transmitted per communication cycle over a communication channel dedicated to the word such that the N channels can transmit K words in parallel.

Abstract: The electronic architecture carries out the management of the functions of a vehicle, the functions being implemented via a set of sensors and actuators, the architecture comprising at least: a central computer; a real-time communication network; a set of interface modules, each module: aggregating signals from at least one of the sensors and sending the signals to the central computer via the communication network; and/or distributing control signals to at least one of the actuators; the central computer driving the actuators according to the signals from the sensors, the control signals for the actuators being sent to the interface modules via the communication network.

Abstract: A neuron circuit is capable of producing a weighted sum of digitized input signals and applying an activation function to the weighted sum so as to produce a digitized activation signal as output. The circuit includes at least: one multiplier multiplying each input signal (x1 to xn) with a weight value (w1j to wnj), one accumulator accumulating the results of the multiplier so as to produce the weighted sum, and one activation unit executing the activation function. The activation unit comprises at least one shift unit and at least one saturation unit capable of approximating a non-linear activation function. The result of the approximated activation function is obtained by one or more arithmetic shifts applied to the weighted sum.

Abstract: A circuit for generating twiddle factors for an NTT processor. The circuit includes a cache management manager, a modular multipliers bank, and a central controller. The cache management module includes a local controller and a cache memory in which operands are stored for calculating future twiddle factors. The modular multipliers bank includes an interconnection matrix at the input distributing operands on the modular multiplier inputs. The circuit can be configured to minimise the size of the cache memory and/or reduce the latency of the twiddle factor sequence calculation. Finally, the generating circuit may include several calculation management modules sharing the same modular multipliers bank to generate sequences of twiddle factors on several finite fields.

Abstract: The present invention relates to a stream-based NTT processor comprising: a plurality (K) of processing stages (210k, k=0, . . . , K?1) organised in a pipeline (210); a plurality (G+1) of memory banks (220g, g=0, . . . , G); a read management module (260) for reading, within one memory) of a memory bank (220g) of the processor, sets of twiddle factors intended for parameterising a processing stage (210k); a write management module (270) for receiving, in the form of successive blocks, a set of twiddle factors and writing said sets of twiddle factors into the memories of a memory bank, the writing being carried out cyclically in the memory banks, each new set of twiddle factors being written into a new memory bank; and a control module for controlling the writing and reading of twiddle factors as well as the progression of data blocks through the processing stages.

Abstract: A circuit comprises a series of calculating blocks that can each implement a group of neurons; a transformation block that is linked to the calculating blocks by a communication means and that can be linked at the input of the circuit to an external data bus, the transformation block transforming the format of the input data and transmitting the data to said calculating blocks by means of K independent communication channels, an input data word being cut up into sub-words such that the sub-words are transmitted over multiple successive communication cycles, one sub-word being transmitted per communication cycle over a communication channel dedicated to the word such that the N channels can transmit K words in parallel.

Abstract: A neuron circuit is capable of producing a weighted sum of digitized input signals and applying an activation function to the weighted sum so as to produce a digitized activation signal as output. The circuit includes at least: one multiplier multiplying each input signal (x1 to xn) with a weight value (w1j to wnj), one accumulator accumulating the results of the multiplier so as to produce the weighted sum, and one activation unit executing the activation function. The activation unit comprises at least one shift unit and at least one saturation unit capable of approximating a non-linear activation function. The result of the approximated activation function is obtained by one or more arithmetic shifts applied to the weighted sum.

Abstract: A compilation system for at least one instruction flow to be executed on a target circuit comprises a hardware acceleration circuit performing the functions of loading a set of at least one portion of said flow to a memory internal to the circuit and of decoding the set; the instructions resulting from the loading and from the decoding being transmitted to a programmable core operating in parallel to the hardware acceleration circuit, the programmable core producing the transcription of the decoded instructions into a machine code suitable for execution on the target circuit.

Abstract: A hardware accelerator for handling red-black trees, each node of a tree including a binary color indicator, a key and the addresses of a parent node and two children nodes, the accelerator including at least two registers termed node registers, capable of storing the set of data fields of two nodes of a tree; and logic units configured for receiving from a processor at least one input data item selected from an address of a tree node and a reference key, as well as at least one instruction to be executed; for executing the instruction by combining elementary instructions on the data stored in the node registers and for supplying to the processor at least one output data item including an address of a node. A processor and computer system including such a hardware accelerator is provided.

Abstract: A compilation system for at least one instruction flow to be executed on a target circuit comprises a hardware acceleration circuit performing the functions of loading a set of at least one portion of said flow to a memory internal to the circuit and of decoding the set; the instructions resulting from the loading and from the decoding being transmitted to a programmable core operating in parallel to the hardware acceleration circuit, the programmable core producing the transcription of the decoded instructions into a machine code suitable for execution on the target circuit.