Patents by Inventor Alexandre Castellane

Alexandre Castellane has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Process for producing electrical-connections on a semiconductor package, and semiconductor package
    Patent number: 6528407
    Abstract: Process for producing electrical-connections on a semiconductor package containing an integrated-circuit chip and with an external protective layer having apertures that least partly expose metal electrical-connection regions, and semiconductor package provided with such metal electrical-connections. The apertures having walls are filled with a metal electrical-connection layer covering at least their walls. A metal solder drop is soldered to the connection layer so that it is not in contact with the external protective layer.
    Type: Grant
    Filed: October 6, 2000
    Date of Patent: March 4, 2003
    Assignee: STMicroelectronics S.A.
    Inventors: Luc Petit, Alexandre Castellane
  • Semiconductor package and method of manufacturing the same
    Patent number: 6312975
    Abstract: A semiconductor package having an encapsulation that encapsulates an integrated circuit chip and an external lead frame for the chip. Multiple connection leads project from the periphery of the encapsulation. At least one external face of the encapsulation is covered with a layer of electrically conductive material, and the conducting material layer has at least one lateral extension that electrically contacts at least one of the projecting connection leads. A method of manufacturing such a semiconductor package is also provided.
    Type: Grant
    Filed: January 26, 1999
    Date of Patent: November 6, 2001
    Assignee: STMicroelectronics S.A.
    Inventors: Rémi Brechignac, Alexandre Castellane