Patents by Inventor Alexandre Fine

Alexandre Fine has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12007858
    Abstract: The invention relates to an electronic system with a built-in computer, designed to execute a source application in response to an external request. The capabilities of the system may include creating a clone of the source application by duplicating the application's executable, which is stored in a separate memory area. The system may then initiate an internal request to run the clone application. The original source and its clone may be executed independently, with the system generating a unified output by comparing the results of both the source and clone applications' execution. The invention provides for an approach to running and comparing software applications, enhancing computational efficiency and reliability.
    Type: Grant
    Filed: February 12, 2021
    Date of Patent: June 11, 2024
    Assignee: THALES
    Inventors: Cedric Balihaut, Alexandre Fine, Sebastien Dotte, Philippe Besnier, Lionel Leroux
  • Publication number: 20240076057
    Abstract: The avionic calculator is suitable for being carried on-board an aircraft and comprises a multi-core processor configured for executing avionic software applications. The processor includes at least one primary core for communicating with at least one avionic equipment distinct from the calculator, each avionic equipment being carried on-board the aircraft and belonging to an avionic domain; at least one secondary core for communicating with at least one electronic device external to the avionic domain; and a tertiary core for performing at least one filtering of a data message received from a respective device external to the avionic domain and intended for a respective avionic equipment of the avionic domain. Each avionic software application being executable by the at least one primary core or the at least one secondary core.
    Type: Application
    Filed: August 24, 2023
    Publication date: March 7, 2024
    Inventors: Stéphane Jean- Mary MONNIER, Alexandre FINE
  • Patent number: 11876912
    Abstract: A method implemented by an onboard avionics computer for executing a plurality of binary codes that are associated with a plurality of sets of metadata, wherein: the plurality of binary codes and the plurality of metadata are hierarchized into a number of levels at least equal to two; a first binary code, of a level, is associated with a first set of metadata of the level, and a second binary code of a lower level, itself associated with a second set of metadata of the lower level; the first set of metadata comprises a data signature, the data comprising at least a first message digest associated with the first binary code, and the second set of metadata comprises a public key; the method comprising the execution, by the second binary code, of the following steps: applying a hash function to obtain a second message digest of the first binary code; decrypting the signature using the public key to obtain the first message digest; authorizing the execution of the binary code, if and only if the first message dig
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: January 16, 2024
    Assignee: THALES
    Inventors: Stéphane Monnier, Alexandre Fine
  • Publication number: 20230353536
    Abstract: The gateway, which connects a low-trust domain (12) and a high-trust domain (13) of an avionics computing infrastructure, provides a plurality of security functions, each function being performed by a data processing node. The gateway comprises, connected in series along a filtering chain of a data flow received from the low-trust domain: a firewall data processing node (4); a protocol break data processing node (5); a master data processing node (1) and an inverse protocol break data processing node (6), the gateway further including a security data processing node (2) connected to each of the data processing nodes of the filtering chain, the different data processing nodes being physically segregated.
    Type: Application
    Filed: April 26, 2023
    Publication date: November 2, 2023
    Inventors: Stéphane Monnier, Alexandre Noinski, Alexandre Fine
  • Publication number: 20230153212
    Abstract: The invention relates to an electronic system comprising an electronic computer, in the presence of an external request to execute a source application whose executable has been previously loaded within a first dedicated area of the memory, being at least configured to: instantiate a clone application of the source application by: duplicating the executable of the source application to create the executable of the clone application, and by storing it in a second area of the memory distinct from the one dedicated to the source application, and by generating a request, internal to the computer, to execute said at least one clone application, execute the source and clone(s) applications independently, generate a single output based on comparing the result of the execution of the source and clone(s) applications.
    Type: Application
    Filed: February 12, 2021
    Publication date: May 18, 2023
    Applicant: THALES
    Inventors: Cedric BALIHAUT, Alexandre FINE, Sebastien DOTTE, Philippe BESNIER, Lionel LEROUX
  • Patent number: 11651543
    Abstract: This method for generating graphic surfaces to be displayed on a screen is implemented by a graphics processor and comprises: generating a first graphic surface to be displayed on the screen; switching between generating the first graphic surface and generating a second graphic surface; generating the second graphic surface to be displayed on the screen; the switching including saving a graphic execution context of the first graphic surface; and if the generation of the second graphic surface had been interrupted during a preceding switch with the generation of another graphic surface, restoring a graphic execution context of the second graphic surface, the restored context having been saved during said preceding switch.
    Type: Grant
    Filed: January 11, 2021
    Date of Patent: May 16, 2023
    Assignee: THALES
    Inventors: Alexandre Fine, Nicolas Levasseur, Yannik Breuil
  • Patent number: 11467880
    Abstract: A method for access to the shared resources of a computer platform including a multicore processor, shared resources between first partitions according to which requests to access the shared resources emitted by the first partitions are sent to a second partition that, during its execution on the processor, performs said accesses; multiple cores are reserved synchronously for the execution of the second access partition during a predetermined time; the separate accesses to separate shared resources done by the second partition having to be done by separate reserved cores; and all of the accesses to a shared resource done by the second access partition having to be executed, during said predetermined time, by a single core among the reserved cores.
    Type: Grant
    Filed: September 10, 2020
    Date of Patent: October 11, 2022
    Assignee: THALES
    Inventors: Gordon Sanderson, Alexandre Fine
  • Publication number: 20220078021
    Abstract: A method implemented by an onboard avionics computer for executing a plurality of binary codes that are associated with a plurality of sets of metadata, wherein: the plurality of binary codes and the plurality of metadata are hierarchized into a number of levels at least equal to two; a first binary code, of a level, is associated with a first set of metadata of the level, and a second binary code of a lower level, itself associated with a second set of metadata of the lower level; the first set of metadata comprises a data signature, the data comprising at least a first message digest associated with the first binary code, and the second set of metadata comprises a public key; the method comprising the execution, by the second binary code, of the following steps: applying a hash function to obtain a second message digest of the first binary code; decrypting the signature using the public key to obtain the first message digest; authorizing the execution of the binary code, if and only if the first message dig
    Type: Application
    Filed: August 31, 2021
    Publication date: March 10, 2022
    Inventors: Stéphane MONNIER, Alexandre FINE
  • Patent number: 11256545
    Abstract: This system on chip comprises a plurality of master resources, a plurality of slave resources, a plurality of arbitration levels, each arbitration level being able to control the access of at least one master resource to at least one slave resource, each master resource being able to send requests to at least one slave resource according to a bandwidth associated with this slave resource and this master resource. The system is characterized by further comprising control means configured to control each bandwidth associated with each slave resource as a function of the capacity of this slave resource to process the requests originating from the master resource corresponding to this bandwidth.
    Type: Grant
    Filed: April 2, 2020
    Date of Patent: February 22, 2022
    Assignee: THALES
    Inventors: Pierrick Lamour, Alexandre Fine
  • Patent number: 11237573
    Abstract: The invention relates to a method for securing the operation of a synthetic viewing system of an aircraft. This method comprises the steps of determining at least one control object in the field of view of the synthetic vision system and determining at least one control point belonging to each control object and verifying the consistency of the display of the synthetic vision system. The verification step comprises the sub-steps of recovering a first position corresponding to the displayed position of each control point on the corresponding outline on the display of the synthetic vision system, determining a second position of each control point on the display of the synthetic vision system and comparing the first and second positions.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: February 1, 2022
    Assignee: THALES
    Inventors: Thierry Ganille, Emmanuel Monvoisin, Alexandre Fine, Pierre Mariani, Hélène Misson
  • Patent number: 11205288
    Abstract: This graphics processor comprises: a generating module configured to generate at least one set of pixel(s) to be displayed; a display module connected to the generating module, the display module being configured to display each set of pixel(s) on a screen; and a monitoring unit integrated into the generating module, the monitoring unit being configured to determine a list of graphic context information item(s) for at least one pixel and to deliver said list to an external electronic supervision device, able to be connected to the graphics processor.
    Type: Grant
    Filed: June 15, 2020
    Date of Patent: December 21, 2021
    Assignee: THALES
    Inventors: Alexandre Fine, Eric Filliatre, Nicolas Levasseur
  • Patent number: 11100897
    Abstract: The invention relates to a method for verifying a character to be displayed on a screen, compared to a reference character. The character to be displayed and the reference character each comprise at least several characteristic points. The method comprises: a) determining a barycenter of the characteristic points of the character to be displayed, b) computing geometric coordinates of each characteristic point of the character to be displayed in a coordinate system centered on the determined barycenter, and c) computing a deviation between the character to be displayed and the reference character, as a function of the geometric coordinates computed for the character to be displayed and predetermined geometric coordinates for the reference character. The character to be displayed is considered correct only if the computed deviation is below the predetermined threshold.
    Type: Grant
    Filed: June 18, 2020
    Date of Patent: August 24, 2021
    Assignee: THALES
    Inventors: Alexandre Fine, Philippe Neto, Siegfried Rouzes
  • Publication number: 20210217221
    Abstract: This method for generating graphic surfaces to be displayed on a screen is implemented by a graphics processor and comprises: generating a first graphic surface to be displayed on the screen; switching between generating the first graphic surface and generating a second graphic surface; generating the second graphic surface to be displayed on the screen; the switching including saving a graphic execution context of the first graphic surface; and if the generation of the second graphic surface had been interrupted during a preceding switch with the generation of another graphic surface, restoring a graphic execution context of the second graphic surface, the restored context having been saved during said preceding switch.
    Type: Application
    Filed: January 11, 2021
    Publication date: July 15, 2021
    Inventors: Alexandre FINE, Nicolas LEVASSEUR, Yannik BREUIL
  • Publication number: 20210192675
    Abstract: This graphics processor unit is intended to be connected to a multi-core central processor unit having N distinct cores, N being an integer greater than or equal to 2, and comprises a memory storage unit. The memory storage unit comprises a reserved space for storing N sets of descriptor(s), each set of descriptor(s) being associated with a respective core of the multi-core central processor unit, each descriptor identifying a batch of resource(s) of the graphics processor unit for the display of data by a software application intended to be executed via said respective core. The graphics processor unit further comprises a sequencer configured to successively process the descriptors stored in the reserved storage space.
    Type: Application
    Filed: December 14, 2020
    Publication date: June 24, 2021
    Inventor: Alexandre FINE
  • Publication number: 20210081251
    Abstract: A method for access to the shared resources of a computer platform including a multicore processor, shared resources between first partitions according to which requests to access the shared resources emitted by the first partitions are sent to a second partition that, during its execution on the processor, performs said accesses; multiple cores are reserved synchronously for the execution of the second access partition during a predetermined time; the separate accesses to separate shared resources done by the second partition having to be done by separate reserved cores; and all of the accesses to a shared resource done by the second access partition having to be executed, during said predetermined time, by a single core among the reserved cores.
    Type: Application
    Filed: September 10, 2020
    Publication date: March 18, 2021
    Inventors: Gordon Sanderson, Alexandre Fine
  • Publication number: 20210082166
    Abstract: This graphics processor comprises: a generating module configured to generate at least one set of pixel(s) to be displayed; a display module connected to the generating module, the display module being configured to display each set of pixel(s) on a screen; and a monitoring unit integrated into the generating module, the monitoring unit being configured to determine a list of graphic context information item(s) for at least one pixel and to deliver said list to an external electronic supervision device, able to be connected to the graphics processor.
    Type: Application
    Filed: June 15, 2020
    Publication date: March 18, 2021
    Inventors: Alexandre FINE, Eric FILLIATRE, Nicolas LEVASSEUR
  • Patent number: 10915363
    Abstract: A resource sharing controller adapted for operating in a computer platform further comprising a data storage medium and software applications comprising access commands to the storage medium, adapted, as a function of a respective portion allocated to each application, of a maximum access capacity to the storage medium, as a function of a list of next commands of access to the storage medium of each application and further of the theoretical maximum performance times of said commands, for selecting, for each application and for a next temporal cycle for access to the storage medium, the next commands to be implemented and for successively distributing, during said next temporal cycle, the access to each application for the implementation of said selected commands.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: February 9, 2021
    Assignee: THALES
    Inventors: David Houlbert, Alexandre Fine, Nicolas Dubois, Frederic Sanson, Laurent Jardin
  • Publication number: 20200410959
    Abstract: The invention relates to a method for verifying a character to be displayed on a screen, compared to a reference character. The character to be displayed and the reference character each comprise at least several characteristic points. The method comprises: a) determining a barycenter of the characteristic points of the character to be displayed, b) computing geometric coordinates of each characteristic point of the character to be displayed in a coordinate system centered on the determined barycenter, and c) computing a deviation between the character to be displayed and the reference character, as a function of the geometric coordinates computed for the character to be displayed and predetermined geometric coordinates for the reference character. The character to be displayed is considered correct only if the computed deviation is below the predetermined threshold.
    Type: Application
    Filed: June 18, 2020
    Publication date: December 31, 2020
    Inventors: Alexandre FINE, Philippe NETO, Siegfried ROUZES
  • Patent number: 10853279
    Abstract: The invention relates to a system for accessing a shared resource belonging to a hardware platform comprising a plurality of master processing units, each master processing unit being able to exploit a shared resource during an execution of a process, each shared resource having an associated maximum bandwidth. For at least one shared resource, the system includes a counter of a number of data transfers between said master processing unit and said shared resource, and a comparator suitable for comparing the number of transfers to a bandwidth limit, which is a fraction of said maximum bandwidth, associated with said shared resource, and a pacing unit suitable for resetting each counter after a time period of predetermined duration has elapsed.
    Type: Grant
    Filed: September 20, 2019
    Date of Patent: December 1, 2020
    Assignee: THALES
    Inventors: Pierrick Lamour, Alexandre Fine
  • Publication number: 20200319926
    Abstract: This system on chip comprises a plurality of master resources, a plurality of slave resources, a plurality of arbitration levels, each arbitration level being able to control the access of at least one master resource to at least one slave resource, each master resource being able to send requests to at least one slave resource according to a bandwidth associated with this slave resource and this master resource. The system is characterized by further comprising control means configured to control each bandwidth associated with each slave resource as a function of the capacity of this slave resource to process the requests originating from the master resource corresponding to this bandwidth.
    Type: Application
    Filed: April 2, 2020
    Publication date: October 8, 2020
    Inventors: Pierrick LAMOUR, Alexandre Fine