Abstract: The multispectral detection device comprises first and second photodetectors sensitive to two different wavelengths. The two photodetectors are connected to two integration capacitors of two different readout circuits. Two reset circuits are configured so as to initialise the two integration capacitors separately. A first synchronisation circuit is connected to the first readout circuit and to the synchronisation signal and clock signal generators. The first synchronisation circuit is configured in such a way as to define the frame by detection of a leading edge of the synchronisation signal, count the number of occurrences of a trailing edge of the clock signal, initiate or terminate a data acquisition phase when the number of occurrences of trailing edges is equal to a threshold value recorded in a register of the first synchronisation circuit.

Abstract: The multispectral detection device comprises first and second photodetectors sensitive to two different wavelengths. The two photodetectors are connected to two integration capacitors of two different readout circuits. Two reset circuits are configured so as to initialise the two integration capacitors separately. A first synchronisation circuit is connected to the first readout circuit and to the synchronisation signal and clock signal generators. The first synchronisation circuit is configured in such a way as to define the frame by detection of a leading edge of the synchronisation signal, count the number of occurrences of a trailing edge of the clock signal, initiate or terminate a data acquisition phase when the number of occurrences of trailing edges is equal to a threshold value recorded in a register of the first synchronisation circuit.

Abstract: A pixel comprises a photodetector and a control circuit. The pixel is provided with an output terminal designed to connect an analysis circuit. The photodetector is configured to have two different operating modes associated with different biasing conditions. A switch connecting the photodetector to the output terminal of the pixel and a circuit for a connecting/disconnecting the control circuit with the output terminal of the pixel and with the photodetector allow to switch between the two operating modes. A comparator compares the voltage across the capacitive load with respect to a threshold value and outputs first and second signals according to the comparison. The comparator is connected to the circuit for connecting/disconnecting the control circuit and to the switch.

Abstract: A very high speed low power receiver equalization system for non-return-to-zero transmission is disclosed. The equalizer comprises a three stage architecture, preferably controlled by three main parameters, the low frequency gain controlled through Rfb, the peaking frequency settled by the capacitor Cfpk, and the variable peak boosting Gpk which provides the equalizer transfer function and the optimum controls of the signal gain characteristic in order to compensate the ISI at the receiver input and consequently allow High speed, reliable links.

Abstract: There is described an improved receiver which first comprises an analog input amplifier a sample and hold differential circuit and two stages of differential comparators that are connected in series, wherein the first stage consists of two comparators and the second stage of one comparator. By properly activating the switches with signals generated by a dedicated control logic, the input differential signal is sampled in the sample and hold circuit to generate first and second differential signals. The first differential signal holds a first state and the second differential signal propagates the second state. As result, the signal output by the second comparator stage reflects the differential offset minus the offset compensation.

Abstract: There is described an improved receiver which first comprises an analog input amplifier a sample and hold differential circuit and two stages of differential comparators that are connected in series, wherein the first stage consists of two comparators and the second stage of one comparator. By properly activating the switches with signals generated by a dedicated control logic, the input differential signal is sampled in the sample and hold circuit to generate first and second differential signals. The first differential signal holds a first state and the second differential signal propagates the second state. As result, the signal output by the second comparator stage reflects the differential offset minus the offset compensation.

Abstract: A differential sampling circuit is configured around a differential operational amplifier and is provided with a pair of switched-capacitor networks, each including an circuit block, to generate the real value of the differential input signal DC offset at each system clock cycle. During the first half cycle, the differential input signal pair (Vin+,Vin?) is sampled and the holding capacitors in each network are charged. During the second half cycle, the differential input signal pair is sampled again and the holding capacitors are further charged. At the end of the cycle, the charges held in the holding capacitors are applied to the differential operational amplifier, so that the differential output signal is equal to the real differential input signal DC offset value.

Abstract: A differential sampling circuit is configured around a differential operational amplifier and is provided with a pair of switched-capacitor networks, each including an circuit block, to generate the real value of the differential input signal DC offset at each system clock cycle. During the first half cycle, the differential input signal pair (Vin+,Vin−) is sampled and the holding capacitors in each network are charged. During the second half cycle, the differential input signal pair is sampled again and the holding capacitors are further charged. At the end of the cycle, the charges held in the holding capacitors are applied to the differential operational amplifier, so that the differential output signal is equal to the real differential input signal DC offset value.