Abstract: In order to detect a faulty error correcting unit (2) in an embedded system, wherein the error correcting unit (2) receives output data from a data source (20) and determines, whether the received data are incorrect, and wherein if the received data are incorrect, the error correcting unit (2) is expected to correct at least one error within the received data, output the corrected data and manipulate an error vector (4), a method and a system (Ia) are suggested that enable to compare the output data of the error correcting unit (2) with at least one reference data, wherein the at least one reference data originate at least indirectly from the data source (20). Both, the error vector (4) and the result of the comparison are input to a plausibility test in order to decide, whether the error correcting unit (2) is faulty. According to the result of the plausibility test, a failure vector (7) is manipulated in order to indicate whether a failure in the error correcting unit (2) is detected.

Abstract: Safe operation in a processor may be verified by making use of an execution trace module that is normally only used for testing and software development. During operation of the processor in the field, a sequence of instructions may be executed the processor. A portion of the execution is traced to form a sequence of trace data. The sequence of trace data is compressed to form a checksum. The checksum is compared to a reference checksum, and an execution error is indicated when the checksum does not match the reference checksum.

Abstract: In order to detect a faulty error correcting unit (2) in an embedded system, wherein the error correcting unit (2) receives output data from a data source (20) and determines, whether the received data are incorrect, and wherein if the received data are incorrect, the error correcting unit (2) is expected to correct at least one error within the received data, output the corrected data and manipulate an error vector (4), a method and a system (Ia) are suggested that enable to compare the output data of the error correcting unit (2) with at least one reference data, wherein the at least one reference data originate at least indirectly from the data source (20). Both, the error vector (4) and the result of the comparison are input to a plausibility test in order to decide, whether the error correcting unit (2) is faulty. According to the result of the plausibility test, a failure vector (7) is manipulated in order to indicate whether a failure in the error correcting unit (2) is detected.

Abstract: A system comprises processing logic. The system also comprises a first interrupt controller coupled to the processing logic and configured to manage interrupts provided to the processing logic. The system further comprises a second interrupt controller coupled to the first interrupt controller. The second interrupt controller is programmable to distribute received interrupts to the first interrupt controller via different output ports.

Abstract: In a bit-accessible memory, a read-modify-write instruction is replaced by an operation with a single memory access. A first mirror memory is identified by a first address OFFSET of the actual memory address. A SET signal logic process is performed when the first mirror memory is addressed. A second mirror memory is identified by a second address offset. A CLEAR signal logic process is performed when the second address offset is used. Transferring the mask used for the read-modify-write operation along with the address, a single predetermined memory location is enabled. The write data bus has logic “1”s applied to all conductors for a SET operation and all logic “0”s for the Clear operation. Only the predetermined memory location is enabled. Thus the correct logic signal is stored in the only enabled location, the predetermined location identified by the mask. In the absence of the OFFSET signal, a normal write operation is performed for the memory access.

Abstract: In order to insure accurate transmission of logic signal, the logic signal and its complement are transmitted between a central processing unit and a peripheral unit. The logic signal and its complement are both used to reconstruct the original logic signal. When an error has occurred in either the logic signal or its complement, an EXCEPTION signal is generated.

Abstract: To expedite the response to an interrupt instruction, an interrupt identification component monitors the execution unit of the central processing unit. When an interrupt instruction is identified, the interrupt identification component forwards this information through a dedicated port to the exception handler, the exception handler storing the procedures that respond to the interrupt instruction. In response to the signals from the interrupt identification unit, the exception handler forwards the responsive procedure to the central processing unit. In this manner, the execution of the interrupt procedure is expedited.