Patents by Inventor Alexandre Raymond

Alexandre Raymond has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11888586
    Abstract: A low-latency network device and method for treating serial data comprising an oscillator generating a device-wide clock; a receiving physical medium attachment (PMA) having an internal data width, a symbol timing synchronization module configured to receive the parallelized sample stream; and detect therefrom synchronized bit values corresponding to bit values of the received serial data; and a physical convergence sublayer (PCS). The PMA is configured to receive the serial data, deserialize the serial data based on the device-wide clock and internal data width, whereby the received serial data is oversampled, the oversampling of the received serial data being asynchronous relative to a timing of the received serial data, and output a parallelized sample stream. The PCS is configured to receive the synchronized bit values; and delineate packets therefrom to provide packet-delineated parallelized data. The PMA, the symbol timing synchronization module and the PCS are all driven by the device-wide clock.
    Type: Grant
    Filed: June 15, 2022
    Date of Patent: January 30, 2024
    Inventor: Alexandre Raymond
  • Publication number: 20230044462
    Abstract: A low-latency network device and method for treating serial data comprising an oscillator generating a device-wide clock; a receiving physical medium attachment (PMA) having an internal data width, a symbol timing synchronization module configured to receive the parallelized sample stream; and detect therefrom synchronized bit values corresponding to bit values of the received serial data; and a physical convergence sublayer (PCS). The PMA is configured to receive the serial data, deserialize the serial data based on the device-wide clock and internal data width, whereby the received serial data is oversampled, the oversampling of the received serial data being asynchronous relative to a timing of the received serial data, and output a parallelized sample stream. The PCS is configured to receive the synchronized bit values; and delineate packets therefrom to provide packet-delineated parallelized data. The PMA, the symbol timing synchronization module and the PCS are all driven by the device-wide clock.
    Type: Application
    Filed: June 15, 2022
    Publication date: February 9, 2023
    Inventor: Alexandre Raymond
  • Patent number: 11328368
    Abstract: A method involving the use of a system is disclosed. The system comprises a processor and an associated memory. The processor executes stored instructions and connects via electronic communication means to create and suggest social events with an associated list of attendees, time range, activity, and location. These events may come into being solely as a result of the system. The attendees are drawn from users with a profile comprising periods of time for which the user is available, personal interests and the identities of persons with whom the user is personally acquainted.
    Type: Grant
    Filed: January 8, 2019
    Date of Patent: May 10, 2022
    Inventor: Alexandre Raymond Labrie
  • Patent number: 10447463
    Abstract: An ultra-low latency communication device includes a clock recovery module, a de-serializer module, an FPGA fabric and a serializer module. The clock recovery module receives an incoming electrical physical layer serial signal and recovers a recovered clock signal therefrom. The de-serializer module converts the incoming electrical physical layer serial signal to an incoming electrical physical layer parallel signal according to driving signals generated based on the recovered clock signal. The FPGA fabric processes the incoming electrical physical layer parallel signal to output an incoming data-link layer parallel signal, receives an outgoing data-link layer parallel signal generated based on electronic information contained in the incoming data-link layer parallel signal, and processes the outgoing data-link layer parallel signal to output an outgoing electrical physical layer parallel signal.
    Type: Grant
    Filed: July 13, 2018
    Date of Patent: October 15, 2019
    Assignee: ORTHOGONE TECHNOLOGIES INC.
    Inventor: Alexandre Raymond
  • Publication number: 20190020466
    Abstract: An ultra-low latency communication device includes a clock recovery module, a de-serializer module, an FPGA fabric and a serializer module. The clock recovery module receives an incoming electrical physical layer serial signal and recovers a recovered clock signal therefrom. The de-serializer module converts the incoming electrical physical layer serial signal to an incoming electrical physical layer parallel signal according to driving signals generated based on the recovered clock signal. The FPGA fabric processes the incoming electrical physical layer parallel signal to output an incoming data-link layer parallel signal, receives an outgoing data-link layer parallel signal generated based on electronic information contained in the incoming data-link layer parallel signal, and processes the outgoing data-link layer parallel signal to output an outgoing electrical physical layer parallel signal.
    Type: Application
    Filed: July 13, 2018
    Publication date: January 17, 2019
    Inventor: Alexandre Raymond
  • Patent number: 9176927
    Abstract: A polar code decoder includes: processing elements each receiving a pair of input values and applying a first or a second predetermined mathematical function depending on a provided function control signal; a first memory that stores at least one of the outputs from processing elements and a plurality of channel values relating to a received polar code to be decoded; a second memory that stores indices of a plurality of frozen bits each representing a bit within an information-bit vector of the polar code being decoded; and a computation block that receives a plurality of inputs from a portion of the processing elements and generates an output that is can be set to a predetermined frozen value or to a calculated value, depending on whether a current index of the bit being decoded is indicated as frozen or not frozen.
    Type: Grant
    Filed: November 8, 2012
    Date of Patent: November 3, 2015
    Assignees: The Royal Institution for the Advancement of Learning/McGill University, The Regents of the University of California
    Inventors: Warren Gross, Gabi Sarkis, Alexandre Raymond, Camille Leroux, Ido Tal, Alexander Vardy
  • Publication number: 20130117344
    Abstract: Coding within noisy communications channels is essential but a theoretical maximum rate defines the rate at which information can be reliably transmitted on this noisy channel. Capacity-achieving codes with an explicit construction eluded researchers until polar codes were proposed. However, whilst asymptotically reaching channel capacity these require increasing code lengths, and hence increasingly complex hardware implementations. It would be beneficial to address architectures and decoding processes to reduce polar code decoder complexity both in terms of the number of processing elements required, but also the number of memory elements and the number of steps required to decode a codeword. Beneficially architectures and design methodologies established by the inventors address such issues whilst reducing overall complexity as well as providing methodologies for adjusting decoder design based upon requirements including, but not limited to, cost (e.g. through die area) and speed (e.g.
    Type: Application
    Filed: November 8, 2012
    Publication date: May 9, 2013
    Inventors: Warren Gross, Gabi Sarkis, Alexandre Raymond, Camille Leroux, Ido Tal, Alexander Vardy