Patents by Inventor Alexandre Sansigolo Lujan

Alexandre Sansigolo Lujan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Scan testing and method thereof
    Patent number: 10345379
    Abstract: An integrated circuit includes clock suppression circuitry that can suppress the launch pulse of an at-speed test to prevent scan test data from propagating from an output of a scan latch through a multi-clock cycle combinational logic path to a downstream scan latch during the at-speed test. The integrated circuit can also suppress the capture pulse of an at-speed test to prevents scan test data that is propagated from an upstream scan latch through a multi-cycle combinational logic path from being latched at the downstream latch during the at-speed test.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: July 9, 2019
    Assignee: NXP USA, Inc.
    Inventors: Alexandre Sansigolo Lujan, Milton Hissasi Kataoka, Rubens Takiguti
  • SCAN TESTING AND METHOD THEREOF
    Publication number: 20190154757
    Abstract: An integrated circuit includes clock suppression circuitry that can suppress the launch pulse of an at-speed test to prevent scan test data from propagating from an output of a scan latch through a multi-clock cycle combinational logic path to a downstream scan latch during the at-speed test. The integrated circuit can also suppress the capture pulse of an at-speed test to prevents scan test data that is propagated from an upstream scan latch through a multi-cycle combinational logic path from being latched at the downstream latch during the at-speed test.
    Type: Application
    Filed: November 20, 2017
    Publication date: May 23, 2019
    Inventors: Alexandre Sansigolo Lujan, Milton Hissasi Kataoka, Rubens Takiguti