Patents by Inventor Alexandre Savtchouk

Alexandre Savtchouk has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11561254
    Abstract: Methods of characterizing electrical properties of a semiconductor layer structure on a wafer with topside semiconductor layers on an insulating or semi-insulating substrate, the semiconductor layer structure including a high electron mobility transistor (HEMT) heterostructure with a two-dimensional electron gas (2DEG) at a heterointerface between the semiconductor layers of the heterostructure. The methods include: (a) physically contacting the topside of the wafer within a narrow border zone at an edge of the wafer with a flexible metal cantilever electrode of a contacting device, wherein the flexible metal cantilever electrode contacts one or more of the semiconductor layers exposed at the narrow border zone so that the flexible metal cantilever electrode is in electrical contact with the 2DEG; and (b) applying corona charge bias and measuring a surface voltage of the semiconductor layers using a non-contact probe while maintaining the electrical contact with the 2DEG.
    Type: Grant
    Filed: May 27, 2021
    Date of Patent: January 24, 2023
    Assignee: SEMILAB Semiconductor Physics Laboratory Co., Ltd.
    Inventors: Marshall Wilson, Bret Schrayer, Alexandre Savtchouk, Dmitriy Marinskiy, Jacek Lagowski
  • Publication number: 20220381816
    Abstract: Methods of characterizing electrical properties of a semiconductor layer structure on a wafer with topside semiconductor layers on an insulating or semi-insulating substrate, the semiconductor layer structure including a high electron mobility transistor (HEMT) heterostructure with a two-dimensional electron gas (2DEG) at a heterointerface between the semiconductor layers of the heterostructure. The methods include: (a) physically contacting the topside of the wafer within a narrow border zone at an edge of the wafer with a flexible metal cantilever electrode of a contacting device, wherein the flexible metal cantilever electrode contacts one or more of the semiconductor layers exposed at the narrow border zone so that the flexible metal cantilever electrode is in electrical contact with the 2DEG; and (b) applying corona charge bias and measuring a surface voltage of the semiconductor layers using a non-contact probe while maintaining the electrical contact with the 2DEG.
    Type: Application
    Filed: May 27, 2021
    Publication date: December 1, 2022
    Inventors: Marshall Wilson, Bret Schrayer, Alexandre Savtchouk, Dmitriy Marinskiy, Jacek Lagowski
  • Patent number: 10969370
    Abstract: An example method of characterizing a semiconductor sample includes measuring an initial value, Vin, of a surface potential at a region of a surface of the semiconductor sample, biasing the semiconductor sample to have a target surface potential value (V0) of 2V or less, and depositing a monitored amount of corona charge (?Q1) on the region of the surface after adjusting the surface potential to the target value. The method also includes measuring a first value, V1, of the surface potential at the region after depositing the corona charge, determining the first change of surface potential (?V1=V1?V0), and determining the first capacitance value C1=?Q1/?V1, and characterizing the semiconductor sample based on V0, V1, ?V1, ?Q1 and C1.
    Type: Grant
    Filed: June 5, 2015
    Date of Patent: April 6, 2021
    Assignee: SEMILAB Semiconductor Physics Laboratory Co., Ltd.
    Inventors: Jacek Lagowski, Marshall Wilson, Alexandre Savtchouk, Carlos Almeida, Csaba Buday
  • Publication number: 20180315630
    Abstract: A method for measuring charging of a semiconductor wafer associated with processing the semiconductor wafer includes using a probe assembly at a charge monitoring module to measure a charge on the semiconductor wafer prior to processing the semiconductor wafer using a processing tool, the probe assembly being located proximate to a processing station of the processing tool; transferring the semiconductor wafer from the charge monitoring module to the processing station using an automated wafer handling apparatus; processing the semiconductor wafer at the processing station using the processing tool; transferring the processed wafer from the processing station back to the charge monitoring module; using the probe assembly at the charge monitoring module to measure a charge on the semiconductor wafer after processing the wafer; and analyzing the measured charge on the semiconductor wafer both before and after processing the semiconductor wafer to determine information about charging of the wafer due to processi
    Type: Application
    Filed: May 1, 2018
    Publication date: November 1, 2018
    Inventors: Dmitriy Marinskiy, Andrew Findlay, Bret Schrayer, Jacek Lagowski, Piotr Edelman, Alexandre Savtchouk
  • Publication number: 20160356750
    Abstract: An example method of characterizing a semiconductor sample includes measuring an initial value, Vin, of a surface potential at a region of a surface of the semiconductor sample, biasing the semiconductor sample to have a target surface potential value (V0) of 2V or less, and depositing a monitored amount of corona charge (?Q1) on the region of the surface after adjusting the surface potential to the target value. The method also includes measuring a first value, V1, of the surface potential at the region after depositing the corona charge, determining the first change of surface potential (?V1=V1?V0), and determining the first capacitance value C1=?Q1/?V1, and characterizing the semiconductor sample based on V0, V1, ?V1, ?Q1 and C1.
    Type: Application
    Filed: June 5, 2015
    Publication date: December 8, 2016
    Inventors: Jacek Lagowski, Marshall Wilson, Alexandre Savtchouk, Carlos Almeida, Csaba Buday
  • Patent number: 8093920
    Abstract: Surface photo-voltage measurements are used to accurately determine very long steady state diffusion length of minority carriers and to determine iron contaminant concentrations and other recombination centers in very pure wafers. Disclosed methods use multiple (e.g., at least two) non-steady state surface photovoltage measurements of diffusion length done at multiple (e.g., at least two) modulation frequencies. The measured diffusion lengths are then used to obtain a steady state diffusion length with an algorithm extrapolating diffusion length to zero frequency. The iron contaminant concentration is obtained from near steady state measurement of diffusion length at elevated frequency before and after iron activation. The concentration of other recombination centers can then be determined from the steady state diffusion length and the iron concentration measured at elevated frequency.
    Type: Grant
    Filed: August 21, 2009
    Date of Patent: January 10, 2012
    Assignee: Semiconductor Diagnostics, Inc.
    Inventors: Jacek Lagowski, Alexandre Savtchouk, Marshall D. Wilson
  • Publication number: 20100085073
    Abstract: Surface photo-voltage measurements are used to accurately determine very long steady state diffusion length of minority carriers and to determine iron contaminant concentrations and other recombination centers in very pure wafers. Disclosed methods use multiple (e.g., at least two) non-steady state surface photovoltage measurements of diffusion length done at multiple (e.g., at least two) modulation frequencies. The measured diffusion lengths are then used to obtain a steady state diffusion length with an algorithm extrapolating diffusion length to zero frequency. The iron contaminant concentration is obtained from near steady state measurement of diffusion length at elevated frequency before and after iron activation. The concentration of other recombination centers can then be determined from the steady state diffusion length and the iron concentration measured at elevated frequency.
    Type: Application
    Filed: August 21, 2009
    Publication date: April 8, 2010
    Inventors: Jacek Lagowski, Alexandre Savtchouk, Marshall D. Wilson
  • Publication number: 20090047748
    Abstract: Methods of measuring copper impurities on a silicon surface are disclosed. In certain embodiments, copper is electrically activated by ultra-violet illumination of the surface at room temperature. Activation can enhance the copper contribution to surface recombination and to surface voltage which are measured in a non-contact manner using a ac-surface photovoltage and a vibrating Kelvin-probe, respectively. Differential measurements before and after activation enable the separations of the copper impurities from other surface contaminants.
    Type: Application
    Filed: May 30, 2008
    Publication date: February 19, 2009
    Inventors: Alexandre Savtchouk, Jacek Lagowski, Lubomir L. Jastrzebski, Joseph Nicholas Kochey
  • Patent number: 6815974
    Abstract: Techniques for determining the composition of mixed dielectric layers are disclosed.
    Type: Grant
    Filed: July 14, 2003
    Date of Patent: November 9, 2004
    Assignee: Semiconductor Diagnostics, Inc.
    Inventors: Jacek Lagowski, Marshall D. Wilson, John D'Amico, Alexandre Savtchouk, Lubomir L. Jastrzebski
  • Patent number: 6771091
    Abstract: Techniques for measuring a contact potential difference of a sample at an elevated temperature using a probe designed for room temperature measurement are disclosed. In such measurements, probe damage by excessive heating can be prevented without any probe modifications to include probe cooling. This can be achieved by minimizing the time the probe spends in close proximity to the heated sample. Furthermore, the effect of probe heating by the sample on the probe reading can be corrected by including an additional contact potential difference measurement of a reference plate kept at room temperature in the measurement cycle.
    Type: Grant
    Filed: September 24, 2002
    Date of Patent: August 3, 2004
    Assignee: Semiconductor Diagnostics, Inc.
    Inventors: Jacek J. Lagowski, Piotr Edelman, Frank Gossett, Nick Kochey, Alexandre Savtchouk
  • Publication number: 20040057497
    Abstract: Techniques for measuring a contact potential difference of a sample at an elevated temperature using a probe designed for room temperature measurement are disclosed. In such measurements, probe damage by excessive heating can be prevented without any probe modifications to include probe cooling. This can be achieved by minimizing the time the probe spends in close proximity to the heated sample. Furthermore, the effect of probe heating by the sample on the probe reading can be corrected by including an additional contact potential difference measurement of a reference plate kept at room temperature in the measurement cycle.
    Type: Application
    Filed: September 24, 2002
    Publication date: March 25, 2004
    Inventors: Jacek J. Lagowski, Piotr Edelman, Frank Gossett, Nick Kochey, Alexandre Savtchouk