Abstract: Systems and methods are disclosed for a configurable interconnect address remapper with event detection. For example, an integrated circuit can include a processor core configured to execute instructions. The processor core includes region registers defined by a From Address range and a To Address, a register storing a number of regions defined in the integrated circuit, interrupt enable registers associated with each pair of region registers, and event flags associated with each pair of region registers; an interconnection system handling transactions from the processor core; an interconnect address remapper translating an address associated with a transaction using the one or more pair of region registers; and an interrupt controller receiving an interrupt signal from the interconnect address remapper when the interrupt enable registers are enabled and at least one raised event flags when at least one of the one or more pair of region registers matches the transaction address.

Abstract: Systems and methods are disclosed for transferring data between a memory system and a vector register file. For example, a system may include a vector pipeline including a vector physical register file; a load store unit; one or more pipeline stages configured to decode a vector memory instruction to obtain a macro-operation and dispatch the macro-operation to both the load store unit and the vector pipeline, and a baler circuitry, including a buffer with entries. The vector pipeline is configured to crack the macro-operation into multiple micro-operations. The baler circuitry is configured to implement the multiple micro-operations to transfer data between one or more selected entries of the buffer and respective registers of the vector physical register file. The load store unit is configured to implement the macro-operation to transfer data between one or more addresses in a memory system and the one or more selected entries of the buffer.

Abstract: Systems and methods are disclosed for a configurable interconnect address remapper with event detection. For example, an integrated circuit can include a processor core configured to execute instructions. The processor core includes region registers defined by a From Address range and a To Address, a register storing a number of regions defined in the integrated circuit, interrupt enable registers associated with each pair of region registers, and event flags associated with each pair of region registers; an interconnection system handling transactions from the processor core; an interconnect address remapper translating an address associated with a transaction using the one or more pair of region registers; and an interrupt controller receiving an interrupt signal from the interconnect address remapper when the interrupt enable registers are enabled and at least one raised event flags when at least one of the one or more pair of region registers matches the transaction address.

Abstract: Apparatus and methods which bundle micro-operations with respect to a vector instruction, dynamically allocate register blocks for a vector instruction, and track the registers using valid bits. A method includes decoding, by a decoder, a vector instruction having a length multiplier of at least two into a number of micro-operations less than the length multiplier, allocating, by an issue queue, an issue queue entry to each of the number of micro-operations and executing, by the issue queue with execution units, each of the number of micro-operations a number of times from the issue queue entry to collectively match the length multiplier.

Abstract: Apparatus and methods which bundle micro-operations with respect to a vector instruction, dynamically allocate register blocks for a vector instruction, and track the registers using valid bits. A method includes decoding, by a decoder, a vector instruction having a length multiplier of at least two into a number of micro-operations less than the length multiplier, allocating, by an issue queue, an issue queue entry to each of the number of micro-operations and executing, by the issue queue with execution units, each of the number of micro-operations a number of times from the issue queue entry to collectively match the length multiplier.

Abstract: Apparatus and methods which bundle micro-operations with respect to a vector instruction, dynamically allocate register blocks for a vector instruction, and track the registers using valid bits. A method includes decoding, by a decoder, a vector instruction having a length multiplier of at least two into a number of micro-operations less than the length multiplier, allocating, by an issue queue, an issue queue entry to each of the number of micro-operations and executing, by the issue queue with execution units, each of the number of micro-operations a number of times from the issue queue entry to collectively match the length multiplier.

Abstract: Systems and methods are disclosed for transferring data between a memory system and a vector register file. For example, a system may include a vector pipeline including a vector physical register file; a load store unit; one or more pipeline stages configured to decode a vector memory instruction to obtain a macro-operation and dispatch the macro-operation to both the load store unit and the vector pipeline, and a baler circuitry, including a buffer with entries. The vector pipeline is configured to crack the macro-operation into multiple micro-operations. The baler circuitry is configured to implement the multiple micro-operations to transfer data between one or more selected entries of the buffer and respective registers of the vector physical register file. The load store unit is configured to implement the macro-operation to transfer data between one or more addresses in a memory system and the one or more selected entries of the buffer.

Abstract: Systems and methods are disclosed for a configurable interconnect address remapper with event detection. For example, an integrated circuit can include a processor core configured to execute instructions. The processor core includes region registers defined by a From Address range and a To Address, a register storing a number of regions defined in the integrated circuit, interrupt enable registers associated with each pair of region registers, and event flags associated with each pair of region registers; an interconnection system handling transactions from the processor core; an interconnect address remapper translating an address associated with a transaction using the one or more pair of region registers; and an interrupt controller receiving an interrupt signal from the interconnect address remapper when the interrupt enable registers are enabled and at least one raised event flags when at least one of the one or more pair of region registers matches the transaction address.

Abstract: Processing circuitry for computer memory management includes memory reduction circuitry to implement a memory reduction technique; and reference count information collection circuitry to: access a memory region, the memory region subject to the memory reduction technique; obtain an indication of memory reduction of the memory region; calculate metrics based on the indication of memory reduction of cache lines associated with the memory region; and provide the metrics to a system software component for use in memory management mechanisms.

Abstract: Various systems and methods for computer memory management are described herein. A system includes a memory controller to: monitor utilization of a memory device, the memory device used with a memory compression technique; determine that the utilization of the memory device violates a threshold; and initiate a system interrupt to provoke a response, responsive to the utilization of the memory device violating the threshold.

Abstract: Processing circuitry for computer memory management includes memory reduction circuitry to implement a memory reduction technique; and reference count information collection circuitry to: access a memory region, the memory region subject to the memory reduction technique; obtain an indication of memory reduction of the memory region; calculate metrics based on the indication of memory reduction of cache lines associated with the memory region; and provide the metrics to a system software component for use in memory management mechanisms.

Abstract: Various systems and methods for computer memory management are described herein. A system includes a memory controller to: monitor utilization of a memory device, the memory device used with a memory compression technique; determine that the utilization of the memory device violates a threshold; and initiate a system interrupt to provoke a response, responsive to the utilization of the memory device violating the threshold.