Patents by Inventor Alexandre Xavier DuChateau

Alexandre Xavier DuChateau has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11921908
    Abstract: A method of volume compressed header identification includes reading, by a processing device of a host, compressible data on a sector of a storage volume of a storage array. The method further includes compressing the compressible data to generate compressed data for the sector. The method further includes adding, by the processing device of the host, metadata associated with the storage volume to the compressed data. The method further includes writing the compressed data, including the added metadata, to the sector of the storage volume of the storage array.
    Type: Grant
    Filed: November 23, 2022
    Date of Patent: March 5, 2024
    Assignee: PURE STORAGE, INC.
    Inventors: Yuval Frandzel, Kiron Vijayasankar, Alexandre Xavier Duchateau, Constantine P. Sapuntzakis
  • Patent number: 11720714
    Abstract: An illustrative method includes a data protection system identifying one or more input operations and one or more output operations performed between a source and a storage system, identifying an anomaly in a relationship between the one or more input operations and the one or more output operations, and determining, based on the identifying of the anomaly, that the storage system is possibly being targeted by a security threat.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: August 8, 2023
    Assignee: Pure Storage, Inc.
    Inventors: Ethan L. Miller, Ronald Karr, Alexandre Xavier Duchâteau, Constantine P Sapuntzakis
  • Publication number: 20230087441
    Abstract: A method of volume compressed header identification includes reading, by a processing device of a host, compressible data on a sector of a storage volume of a storage array. The method further includes compressing the compressible data to generate compressed data for the sector. The method further includes adding, by the processing device of the host, metadata associated with the storage volume to the compressed data. The method further includes writing the compressed data, including the added metadata, to the sector of the storage volume of the storage array.
    Type: Application
    Filed: November 23, 2022
    Publication date: March 23, 2023
    Inventors: YUVAL FRANDZEL, KIRON VIJAYASANKAR, ALEXANDRE XAVIER DUCHATEAU, CONSTANTINE P. SAPUNTZAKIS
  • Patent number: 11520936
    Abstract: A method of volume compressed header identification includes reading, by a processing device of a host, compressible data on a sector of a storage volume of a storage array. The method further includes compressing the compressible data to generate compressed data for the sector. The method further includes adding, by the processing device of the host, metadata associated with the storage volume to the compressed data. The method further includes writing the compressed data, including the added metadata, to the sector of the storage volume of the storage array.
    Type: Grant
    Filed: December 22, 2020
    Date of Patent: December 6, 2022
    Assignee: Pure Storage, Inc.
    Inventors: Yuval Frandzel, Kiron Vijayasankar, Alexandre Xavier Duchateau, Constantine P. Sapuntzakis
  • Publication number: 20220382917
    Abstract: A method includes compressing data to generate compressed data having a first block size corresponding to a block-size requirement of a client device. The method further includes encrypting the compressed data to generate an encrypted data packet. The method further includes adding, by a processing device, a padding bit pattern to the encrypted data packet to generate a data block for storage, the data block having a second block size determined by a buffer size of a storage array.
    Type: Application
    Filed: August 11, 2022
    Publication date: December 1, 2022
    Inventors: Kiron Vijayasankar, Alexandre Xavier Duchateau, Constantine P. Sapuntzakis, Yuval Frandzel
  • Patent number: 11436378
    Abstract: A method includes compressing data to generate compressed data having a first block size corresponding to a block-size requirement of a client device. The method further includes encrypting the compressed data to generate an encrypted data packet. The method further includes adding, by a processing device, a padding bit pattern to the encrypted data packet to generate a data block for storage, the data block having a second block size determined by a buffer size of a storage array.
    Type: Grant
    Filed: July 30, 2020
    Date of Patent: September 6, 2022
    Assignee: Pure Storage, Inc.
    Inventors: Kiron Vijayasankar, Alexandre Xavier Duchateau, Constantine P. Sapuntzakis, Yuval Frandzel
  • Publication number: 20210216666
    Abstract: An illustrative method includes a data protection system identifying one or more input operations and one or more output operations performed between a source and a storage system, identifying an anomaly in a relationship between the one or more input operations and the one or more output operations, and determining, based on the identifying of the anomaly, that the storage system is possibly being targeted by a security threat.
    Type: Application
    Filed: September 30, 2020
    Publication date: July 15, 2021
    Inventors: Ethan L. Miller, Ronald Karr, Alexandre Xavier Duchâteau, Constantine P Sapuntzakis
  • Patent number: 10901660
    Abstract: A method of volume compressed header identification includes reading, by a processing device of a host, compressible data on a sector of a storage volume of a storage array. The method further includes compressing the compressible data to generate compressed data for the sector. The method further includes adding, by the processing device of the host, metadata associated with the storage volume to the compressed data. The method further includes writing the compressed data, including the added metadata, to the sector of the storage volume of the storage array.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: January 26, 2021
    Assignee: Pure Storage, Inc.
    Inventors: Yuval Frandzel, Kiron Vijayasankar, Alexandre Xavier Duchateau, Constantine P. Sapuntzakis
  • Publication number: 20200364379
    Abstract: A method includes compressing data to generate compressed data having a first block size corresponding to a block-size requirement of a client device. The method further includes encrypting the compressed data to generate an encrypted data packet. The method further includes adding, by a processing device, a padding bit pattern to the encrypted data packet to generate a data block for storage, the data block having a second block size determined by a buffer size of a storage array.
    Type: Application
    Filed: July 30, 2020
    Publication date: November 19, 2020
    Inventors: Kiron Vijayasankar, Alexandre Xavier Duchateau, Constantine P. Sapuntzakis, Yuval Frandzel
  • Patent number: 10831935
    Abstract: A method of encryption management with host-side data reduction includes identifying data to be written to a storage array and compressing the data to generate compressed data. The method further includes encrypting the compressed data to generate an encrypted data packet. The method further includes adding, by a processing device of a host, a padding bit pattern to the encrypted data packet to generate a data block for storage. The method further includes sending the data block to the storage array.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: November 10, 2020
    Assignee: Pure Storage, Inc.
    Inventors: Kiron Vijayasankar, Alexandre Xavier Duchateau, Constantine P. Sapuntzakis, Yuval Frandzel
  • Publication number: 20190065788
    Abstract: A method of encryption management with host-side data reduction includes identifying data to be written to a storage array and compressing the data to generate compressed data. The method further includes encrypting the compressed data to generate an encrypted data packet. The method further includes adding, by a processing device of a host, a padding bit pattern to the encrypted data packet to generate a data block for storage. The method further includes sending the data block to the storage array.
    Type: Application
    Filed: August 29, 2018
    Publication date: February 28, 2019
    Inventors: Kiron Vijayasankar, Alexandre Xavier Duchateau, Constantine P. Sapuntzakis, Yuval Frandzel
  • Patent number: 9971703
    Abstract: Technologies for persistent memory pointer access include a computing device having a persistent memory including one or more nonvolatile regions. The computing device may load a persistent memory pointer having a static region identifier, a segment identifier, and an offset from the persistent memory. The computing device may map the static region identifier to a dynamic region identifier and determine a virtual memory address of the persistent memory pointer target based on the dynamic region identifier, the segment identifier, and the offset. The computing device may load an in-storage representation of a persistent-export pointer from the persistent memory, map the in-storage representation to a runtime representation, and determine a target address of a persistent external data object based on the runtime representation. The computing device may include a compiler to generate output code including persistent memory pointer and/or persistent-export pointer accesses.
    Type: Grant
    Filed: August 9, 2017
    Date of Patent: May 15, 2018
    Assignee: Intel Corporation
    Inventors: Marcelo S. Cintra, Cheng Wang, Youfeng Wu, Alexandre Xavier DuChateau
  • Publication number: 20170337137
    Abstract: Technologies for persistent memory pointer access include a computing device having a persistent memory including one or more nonvolatile regions. The computing device may load a persistent memory pointer having a static region identifier, a segment identifier, and an offset from the persistent memory. The computing device may map the static region identifier to a dynamic region identifier and determine a virtual memory address of the persistent memory pointer target based on the dynamic region identifier, the segment identifier, and the offset. The computing device may load an in-storage representation of a persistent-export pointer from the persistent memory, map the in-storage representation to a runtime representation, and determine a target address of a persistent external data object based on the runtime representation. The computing device may include a compiler to generate output code including persistent memory pointer and/or persistent-export pointer accesses.
    Type: Application
    Filed: August 9, 2017
    Publication date: November 23, 2017
    Inventors: Marcelo S. Cintra, Cheng Wang, Youfeng Wu, Alexandre Xavier DuChateau
  • Patent number: 9767037
    Abstract: Technologies for persistent memory pointer access include a computing device having a persistent memory including one or more nonvolatile regions. The computing device may load a persistent memory pointer having a static region identifier, a segment identifier, and an offset from the persistent memory. The computing device may map the static region identifier to a dynamic region identifier and determine a virtual memory address of the persistent memory pointer target based on the dynamic region identifier, the segment identifier, and the offset. The computing device may load an in-storage representation of a persistent-export pointer from the persistent memory, map the in-storage representation to a runtime representation, and determine a target address of a persistent external data object based on the runtime representation. The computing device may include a compiler to generate output code including persistent memory pointer and/or persistent-export pointer accesses.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: September 19, 2017
    Assignee: Intel Corporation
    Inventors: Marcelo S. Cintra, Cheng Wang, Youfeng Wu, Alexandre Xavier DuChateau
  • Publication number: 20160378679
    Abstract: Technologies for persistent memory pointer access include a computing device having a persistent memory including one or more nonvolatile regions. The computing device may load a persistent memory pointer having a static region identifier, a segment identifier, and an offset from the persistent memory. The computing device may map the static region identifier to a dynamic region identifier and determine a virtual memory address of the persistent memory pointer target based on the dynamic region identifier, the segment identifier, and the offset. The computing device may load an in-storage representation of a persistent-export pointer from the persistent memory, map the in-storage representation to a runtime representation, and determine a target address of a persistent external data object based on the runtime representation. The computing device may include a compiler to generate output code including persistent memory pointer and/or persistent-export pointer accesses.
    Type: Application
    Filed: June 26, 2015
    Publication date: December 29, 2016
    Inventors: Marcelo S. Cintra, Cheng Wang, Youfeng Wu, Alexandre Xavier DuChateau