Patents by Inventor Alexandre Xavier DuChateau
Alexandre Xavier DuChateau has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11921908Abstract: A method of volume compressed header identification includes reading, by a processing device of a host, compressible data on a sector of a storage volume of a storage array. The method further includes compressing the compressible data to generate compressed data for the sector. The method further includes adding, by the processing device of the host, metadata associated with the storage volume to the compressed data. The method further includes writing the compressed data, including the added metadata, to the sector of the storage volume of the storage array.Type: GrantFiled: November 23, 2022Date of Patent: March 5, 2024Assignee: PURE STORAGE, INC.Inventors: Yuval Frandzel, Kiron Vijayasankar, Alexandre Xavier Duchateau, Constantine P. Sapuntzakis
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Patent number: 11720714Abstract: An illustrative method includes a data protection system identifying one or more input operations and one or more output operations performed between a source and a storage system, identifying an anomaly in a relationship between the one or more input operations and the one or more output operations, and determining, based on the identifying of the anomaly, that the storage system is possibly being targeted by a security threat.Type: GrantFiled: September 30, 2020Date of Patent: August 8, 2023Assignee: Pure Storage, Inc.Inventors: Ethan L. Miller, Ronald Karr, Alexandre Xavier Duchâteau, Constantine P Sapuntzakis
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Publication number: 20230087441Abstract: A method of volume compressed header identification includes reading, by a processing device of a host, compressible data on a sector of a storage volume of a storage array. The method further includes compressing the compressible data to generate compressed data for the sector. The method further includes adding, by the processing device of the host, metadata associated with the storage volume to the compressed data. The method further includes writing the compressed data, including the added metadata, to the sector of the storage volume of the storage array.Type: ApplicationFiled: November 23, 2022Publication date: March 23, 2023Inventors: YUVAL FRANDZEL, KIRON VIJAYASANKAR, ALEXANDRE XAVIER DUCHATEAU, CONSTANTINE P. SAPUNTZAKIS
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Patent number: 11520936Abstract: A method of volume compressed header identification includes reading, by a processing device of a host, compressible data on a sector of a storage volume of a storage array. The method further includes compressing the compressible data to generate compressed data for the sector. The method further includes adding, by the processing device of the host, metadata associated with the storage volume to the compressed data. The method further includes writing the compressed data, including the added metadata, to the sector of the storage volume of the storage array.Type: GrantFiled: December 22, 2020Date of Patent: December 6, 2022Assignee: Pure Storage, Inc.Inventors: Yuval Frandzel, Kiron Vijayasankar, Alexandre Xavier Duchateau, Constantine P. Sapuntzakis
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Publication number: 20220382917Abstract: A method includes compressing data to generate compressed data having a first block size corresponding to a block-size requirement of a client device. The method further includes encrypting the compressed data to generate an encrypted data packet. The method further includes adding, by a processing device, a padding bit pattern to the encrypted data packet to generate a data block for storage, the data block having a second block size determined by a buffer size of a storage array.Type: ApplicationFiled: August 11, 2022Publication date: December 1, 2022Inventors: Kiron Vijayasankar, Alexandre Xavier Duchateau, Constantine P. Sapuntzakis, Yuval Frandzel
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Patent number: 11436378Abstract: A method includes compressing data to generate compressed data having a first block size corresponding to a block-size requirement of a client device. The method further includes encrypting the compressed data to generate an encrypted data packet. The method further includes adding, by a processing device, a padding bit pattern to the encrypted data packet to generate a data block for storage, the data block having a second block size determined by a buffer size of a storage array.Type: GrantFiled: July 30, 2020Date of Patent: September 6, 2022Assignee: Pure Storage, Inc.Inventors: Kiron Vijayasankar, Alexandre Xavier Duchateau, Constantine P. Sapuntzakis, Yuval Frandzel
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Publication number: 20210216666Abstract: An illustrative method includes a data protection system identifying one or more input operations and one or more output operations performed between a source and a storage system, identifying an anomaly in a relationship between the one or more input operations and the one or more output operations, and determining, based on the identifying of the anomaly, that the storage system is possibly being targeted by a security threat.Type: ApplicationFiled: September 30, 2020Publication date: July 15, 2021Inventors: Ethan L. Miller, Ronald Karr, Alexandre Xavier Duchâteau, Constantine P Sapuntzakis
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Patent number: 10901660Abstract: A method of volume compressed header identification includes reading, by a processing device of a host, compressible data on a sector of a storage volume of a storage array. The method further includes compressing the compressible data to generate compressed data for the sector. The method further includes adding, by the processing device of the host, metadata associated with the storage volume to the compressed data. The method further includes writing the compressed data, including the added metadata, to the sector of the storage volume of the storage array.Type: GrantFiled: August 30, 2018Date of Patent: January 26, 2021Assignee: Pure Storage, Inc.Inventors: Yuval Frandzel, Kiron Vijayasankar, Alexandre Xavier Duchateau, Constantine P. Sapuntzakis
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Publication number: 20200364379Abstract: A method includes compressing data to generate compressed data having a first block size corresponding to a block-size requirement of a client device. The method further includes encrypting the compressed data to generate an encrypted data packet. The method further includes adding, by a processing device, a padding bit pattern to the encrypted data packet to generate a data block for storage, the data block having a second block size determined by a buffer size of a storage array.Type: ApplicationFiled: July 30, 2020Publication date: November 19, 2020Inventors: Kiron Vijayasankar, Alexandre Xavier Duchateau, Constantine P. Sapuntzakis, Yuval Frandzel
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Patent number: 10831935Abstract: A method of encryption management with host-side data reduction includes identifying data to be written to a storage array and compressing the data to generate compressed data. The method further includes encrypting the compressed data to generate an encrypted data packet. The method further includes adding, by a processing device of a host, a padding bit pattern to the encrypted data packet to generate a data block for storage. The method further includes sending the data block to the storage array.Type: GrantFiled: August 29, 2018Date of Patent: November 10, 2020Assignee: Pure Storage, Inc.Inventors: Kiron Vijayasankar, Alexandre Xavier Duchateau, Constantine P. Sapuntzakis, Yuval Frandzel
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Publication number: 20190065788Abstract: A method of encryption management with host-side data reduction includes identifying data to be written to a storage array and compressing the data to generate compressed data. The method further includes encrypting the compressed data to generate an encrypted data packet. The method further includes adding, by a processing device of a host, a padding bit pattern to the encrypted data packet to generate a data block for storage. The method further includes sending the data block to the storage array.Type: ApplicationFiled: August 29, 2018Publication date: February 28, 2019Inventors: Kiron Vijayasankar, Alexandre Xavier Duchateau, Constantine P. Sapuntzakis, Yuval Frandzel
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Patent number: 9971703Abstract: Technologies for persistent memory pointer access include a computing device having a persistent memory including one or more nonvolatile regions. The computing device may load a persistent memory pointer having a static region identifier, a segment identifier, and an offset from the persistent memory. The computing device may map the static region identifier to a dynamic region identifier and determine a virtual memory address of the persistent memory pointer target based on the dynamic region identifier, the segment identifier, and the offset. The computing device may load an in-storage representation of a persistent-export pointer from the persistent memory, map the in-storage representation to a runtime representation, and determine a target address of a persistent external data object based on the runtime representation. The computing device may include a compiler to generate output code including persistent memory pointer and/or persistent-export pointer accesses.Type: GrantFiled: August 9, 2017Date of Patent: May 15, 2018Assignee: Intel CorporationInventors: Marcelo S. Cintra, Cheng Wang, Youfeng Wu, Alexandre Xavier DuChateau
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Publication number: 20170337137Abstract: Technologies for persistent memory pointer access include a computing device having a persistent memory including one or more nonvolatile regions. The computing device may load a persistent memory pointer having a static region identifier, a segment identifier, and an offset from the persistent memory. The computing device may map the static region identifier to a dynamic region identifier and determine a virtual memory address of the persistent memory pointer target based on the dynamic region identifier, the segment identifier, and the offset. The computing device may load an in-storage representation of a persistent-export pointer from the persistent memory, map the in-storage representation to a runtime representation, and determine a target address of a persistent external data object based on the runtime representation. The computing device may include a compiler to generate output code including persistent memory pointer and/or persistent-export pointer accesses.Type: ApplicationFiled: August 9, 2017Publication date: November 23, 2017Inventors: Marcelo S. Cintra, Cheng Wang, Youfeng Wu, Alexandre Xavier DuChateau
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Patent number: 9767037Abstract: Technologies for persistent memory pointer access include a computing device having a persistent memory including one or more nonvolatile regions. The computing device may load a persistent memory pointer having a static region identifier, a segment identifier, and an offset from the persistent memory. The computing device may map the static region identifier to a dynamic region identifier and determine a virtual memory address of the persistent memory pointer target based on the dynamic region identifier, the segment identifier, and the offset. The computing device may load an in-storage representation of a persistent-export pointer from the persistent memory, map the in-storage representation to a runtime representation, and determine a target address of a persistent external data object based on the runtime representation. The computing device may include a compiler to generate output code including persistent memory pointer and/or persistent-export pointer accesses.Type: GrantFiled: June 26, 2015Date of Patent: September 19, 2017Assignee: Intel CorporationInventors: Marcelo S. Cintra, Cheng Wang, Youfeng Wu, Alexandre Xavier DuChateau
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Publication number: 20160378679Abstract: Technologies for persistent memory pointer access include a computing device having a persistent memory including one or more nonvolatile regions. The computing device may load a persistent memory pointer having a static region identifier, a segment identifier, and an offset from the persistent memory. The computing device may map the static region identifier to a dynamic region identifier and determine a virtual memory address of the persistent memory pointer target based on the dynamic region identifier, the segment identifier, and the offset. The computing device may load an in-storage representation of a persistent-export pointer from the persistent memory, map the in-storage representation to a runtime representation, and determine a target address of a persistent external data object based on the runtime representation. The computing device may include a compiler to generate output code including persistent memory pointer and/or persistent-export pointer accesses.Type: ApplicationFiled: June 26, 2015Publication date: December 29, 2016Inventors: Marcelo S. Cintra, Cheng Wang, Youfeng Wu, Alexandre Xavier DuChateau