Abstract: A two-input amplifier is disclosed. The amplifier can include an amplification path for a first input signal that can have adjustable flatness or high-frequency peaking, and an amplification path for a second input that can be substantially independent of the frequency-shaping aspect of the first-input path. The first-input amplification path can include an operational amplifier as an active device and a plurality of passive elements for frequency shaping. The second-input amplification path can include a device that injects its output current into a node of the first path. The signals of the two paths can be combined and appear substantially independently of each other at the output of the amplifier.

Abstract: A self-biased cascode current mirror/scaler circuit can include a bias FET biased with an input current to generate a gate-source voltage, which can be divided by a bias circuit into a first voltage component (e.g., at a threshold voltage) and a second voltage component (at a FET drain-source saturation voltage or edge of saturation voltage). An input FET of the current mirror/scaler circuit can receive approximately the input current or a function thereof. A gate of the input FET can be biased at the first voltage component in sum with a FET drain-source saturation voltage or edge of saturation voltage of the input FET. A gate of the output FET can be connected to the gate of the input FET. A gate of a cascode FET in series with the output FET can be biased at the first voltage component in sum with the second voltage component in sum with the FET drain-source saturation voltage or edge of saturation voltage of the input FET.

Abstract: The circuit of the present disclosure is a high-speed precision clamp (voltage limiter) for overvoltage or undervoltage protection. One aspect of the circuit includes using a peak detector in the feedback path of a clamp having a super-diode architecture. The resulting circuit performs well for high-speed applications. The peak detector can be replicated (at least in part) to accommodate a multiplicity of phase-shifted input voltages by using only one common peak detection capacitor and ensuring area savings in integrated-circuit implementations.

Abstract: A programmable charge pump, such as for use in CMOS phase-locked loop circuits, is provided. In an example, the charge pump includes a reference stage that provides DC signals to an output stage of the charge pump. The output stage includes output switches for generating output pulses in accordance with external control signals. In an example, loop performance can be improved when an output stage of the charge pump provides a relatively large output impedance. The output switches can be isolated when the charge pump is in an OFF state. For example, respective isolation switches can be used to substantially concurrently switch source and drain terminals for each of the output switches in the charge pump. In an example, a reference stage of the charge pump can provide a buffer for reducing charge-sharing between the output switches and an output node of the output stage.

Abstract: A programmable charge pump, such as for use in CMOS phase-locked loop circuits, is provided. In an example, the charge pump includes a reference stage that provides DC signals to an output stage of the charge pump. The output stage includes output switches for generating output pulses in accordance with external control signals. In an example, loop performance can be improved when an output stage of the charge pump provides a relatively large output impedance. The output switches can be isolated when the charge pump is in an OFF state. For example, respective isolation switches can be used to substantially concurrently switch source and drain terminals for each of the output switches in the charge pump. In an example, a reference stage of the charge pump can provide a buffer for reducing charge-sharing between the output switches and an output node of the output stage.

Abstract: A self-biased cascode current mirror/scaler circuit can include a bias FET biased with an input current to generate a gate-source voltage, which can be divided by a bias circuit into a first voltage component (e.g., at a threshold voltage) and a second voltage component (at a FET drain-source saturation voltage or edge of saturation voltage). An input FET of the current mirror/scaler circuit can receive approximately the input current or a function thereof. A gate of the input FET can be biased at the first voltage component in sum with a FET drain-source saturation voltage or edge of saturation voltage of the input FET. A gate of the output FET can be connected to the gate of the input FET. A gate of a cascode FET in series with the output FET can be biased at the first voltage component in sum with the second voltage component in sum with the FET drain-source saturation voltage or edge of saturation voltage of the input FET.

Abstract: A two-input amplifier is disclosed. The amplifier can include an amplification path for a first input signal that can have adjustable flatness or high-frequency peaking, and an amplification path for a second input that can be substantially independent of the frequency-shaping aspect of the first-input path. The first-input amplification path can include an operational amplifier as an active device and a plurality of passive elements for frequency shaping. The second-input amplification path can include a device that injects its output current into a node of the first path. The signals of the two paths can be combined and appear substantially independently of each other at the output of the amplifier.

Abstract: A current amplifier is disclosed. The circuit has differential input and output and can be implemented in CMOS or bipolar integrated-circuit technologies. The input current is injected into a pair of primary branches, and is re-used at the output of the circuit without changing its natural flow, thus contributing to the overall current gain. A pair of secondary branches is connected to the primary branches in such a way as to provide currents proportional to the input currents according to a scaling factor dictated by the geometry of the transistors. The outputs of the secondary branches are cross-coupled relative to the outputs of the primary branches, in this way ensuring maximum current gain by the summing of the primary and secondary signal currents at the circuit output, without consuming additional DC power.

Abstract: An integrated, fully-differential current-feedback transimpedance operational amplifier circuit is disclosed. The circuit can be configured as a class-AB, low-impedance input stage, followed by an inverter-based, rail-to-rail output stage. For enhancing the open-loop transimpedance gain of the amplifier without consuming additional DC power, the same bias current is used both in the input stage and in a gain-enhancement stage serving as its load. The gain-enhancement stage can be either DC- or AC-coupled to the input of the amplifier. In the case of DC coupling, an output common-mode feedback loop can be used to provide the proper operating voltages in the amplifier.

Abstract: The circuit of the present disclosure is a high-speed precision clamp (voltage limiter) for overvoltage or undervoltage protection. One aspect of the circuit includes using a peak detector in the feedback path of a clamp having a super-diode architecture. The resulting circuit performs well for high-speed applications. The peak detector can be replicated (at least in part) to accommodate a multiplicity of phase-shifted input voltages by using only one common peak detection capacitor and ensuring area savings in integrated-circuit implementations.

Abstract: A current amplifier is disclosed. The circuit has differential input and output and can be implemented in CMOS or bipolar integrated-circuit technologies. The input current is injected into a pair of primary branches, and is re-used at the output of the circuit without changing its natural flow, thus contributing to the overall current gain. A pair of secondary branches is connected to the primary branches in such a way as to provide currents proportional to the input currents according to a scaling factor dictated by the geometry of the transistors. The outputs of the secondary branches are cross-coupled relative to the outputs of the primary branches, in this way ensuring maximum current gain by the summing of the primary and secondary signal currents at the circuit output, without consuming additional DC power.

Abstract: Apparatus and methods for high-frequency low-pass filtering are disclosed. A first resistor is operatively coupled between a first node and a second node. A second resistor is operatively coupled between the second node and a third node. An amplifier circuit has a first input operatively coupled to the third node and a first output operatively coupled to a fourth node. The first output is configured to provide a first output signal. A first complex impedance network is operatively coupled between the fourth node and the third node. A first feedback path is operatively coupled between the fourth node and the second node. The first feedback path is configured to invert at least a portion of the first output signal. The first feedback path is further configured to provide a first feedback capacitance at the second node.

Abstract: Apparatus and methods for high-frequency low-pass filtering are disclosed. A first resistor is operatively coupled between a first node and a second node. A second resistor is operatively coupled between the second node and a third node. An amplifier circuit has a first input operatively coupled to the third node and a first output operatively coupled to a fourth node. The first output is configured to provide a first output signal. A first complex impedance network is operatively coupled between the fourth node and the third node. A first feedback path is operatively coupled between the fourth node and the second node. The first feedback path is configured to invert at least a portion of the first output signal. The first feedback path is further configured to provide a first feedback capacitance at the second node.

Abstract: An integrated, fully-differential current-feedback transimpedance operational amplifier circuit is disclosed. The circuit can be configured as a class-AB, low-impedance input stage, followed by an inverter-based, rail-to-rail output stage. For enhancing the open-loop transimpedance gain of the amplifier without consuming additional DC power, the same bias current is used both in the input stage and in a gain-enhancement stage serving as its load. The gain-enhancement stage can be either DC- or AC-coupled to the input of the amplifier. In the case of DC coupling, an output common-mode feedback loop can be used to provide the proper operating voltages in the amplifier.

Abstract: Embodiments of integrated circuits for use in a broadband tuner are described. In one embodiment, an integrated circuit includes a clock buffer configured to buffer a received clock signal and generate a buffered clock signal. Additionally, the integrated circuit includes a multiphase local oscillator core coupled to the clock buffer and configured to generate a plurality of oscillator signals in response to the buffered clock signal, each of the plurality of oscillator signals being mutually phase shifted. The integrated circuit may also include a plurality of output buffers, each configured to receive one of the plurality of oscillator signals and to produce an output signal suitable for use in a broadband tuner circuit in response to the one of the plurality of oscillator signals.

Abstract: An integrated semiconductor image-rejection mixer having high linearity and high gain. In addition to the components of a classic image-rejection architecture, the present mixer has a high-frequency current-diverting stage that permits the operation of the output stage with high conversion gain and sufficient headroom for good linearity, even in cases where the supply voltage is relatively low (such as 3 V). The conversion gain of the mixer and its image-rejection performance can be changed by changing the load resistances and the elements of the output polyphase network, with minor effects on linearity and no change in power consumption or DC levels. The power consumption of the image-rejection mixer is low because no additional DC current is required for buffers or amplifier stages.