Patents by Inventor Alexandru Romanescu
Alexandru Romanescu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10886419Abstract: A method includes providing a semiconductor structure comprising a varactor region and a field effect transistor region. The varactor region includes a body region in a semiconductor material that is doped to have a first conductivity type. A gate-first process is performed by forming a gate stack over the semiconductor structure. The gate stack includes a layer of gate insulation material and a layer of work function adjustment metal positioned over the layer of gate insulation material. The gate stack is patterned to define a first gate structure over the varactor region and a second gate structure over the field effect transistor region. A source region and a drain region are formed in the field effect transistor region adjacent the second gate structure. The source region and the drain region are doped to have a second conductivity type opposite to the first conductivity type.Type: GrantFiled: March 6, 2018Date of Patent: January 5, 2021Assignee: GLOBALFOUNDRIES Inc.Inventors: Alexandru Romanescu, Christian Schippel, Nicolas Sassiat
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Publication number: 20180198000Abstract: A method includes providing a semiconductor structure comprising a varactor region and a field effect transistor region. The varactor region includes a body region in a semiconductor material that is doped to have a first conductivity type. A gate-first process is performed by forming a gate stack over the semiconductor structure. The gate stack includes a layer of gate insulation material and a layer of work function adjustment metal positioned over the layer of gate insulation material. The gate stack is patterned to define a first gate structure over the varactor region and a second gate structure over the field effect transistor region. A source region and a drain region are formed in the field effect transistor region adjacent the second gate structure. The source region and the drain region are doped to have a second conductivity type opposite to the first conductivity type.Type: ApplicationFiled: March 6, 2018Publication date: July 12, 2018Inventors: Alexandru Romanescu, Christian Schippel, Nicolas Sassiat
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Patent number: 9960284Abstract: A semiconductor structure includes a varactor and a field effect transistor. The varactor includes a body region that includes a semiconductor material and a first gate structure over the body region. The body region is doped to have a first conductivity type. The first gate structure includes a first gate insulation layer and a first work function adjustment metal layer. The field effect transistor includes a source region, a channel region, a drain region and a second gate structure over the channel region. The source region and the drain region are doped to have a second conductivity type that is opposite to the first conductivity type. The second gate structure includes a second gate insulation layer and a second work function adjustment metal layer. The first work function adjustment metal layer and the second work function adjustment metal layer include substantially the same metal.Type: GrantFiled: October 30, 2015Date of Patent: May 1, 2018Assignee: GLOBALFOUNDRIES Inc.Inventors: Alexandru Romanescu, Christian Schippel, Nicolas Sassiat
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Publication number: 20170125610Abstract: A semiconductor structure includes a varactor and a field effect transistor. The varactor includes a body region that includes a semiconductor material and a first gate structure over the body region. The body region is doped to have a first conductivity type. The first gate structure includes a first gate insulation layer and a first work function adjustment metal layer. The field effect transistor includes a source region, a channel region, a drain region and a second gate structure over the channel region. The source region and the drain region are doped to have a second conductivity type that is opposite to the first conductivity type. The second gate structure includes a second gate insulation layer and a second work function adjustment metal layer. The first work function adjustment metal layer and the second work function adjustment metal layer include substantially the same metal.Type: ApplicationFiled: October 30, 2015Publication date: May 4, 2017Inventors: Alexandru Romanescu, Christian Schippel, Nicolas Sassiat
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Integrated circuits with resistor structures formed from gate metal and methods for fabricating same
Patent number: 9530770Abstract: Integrated circuits having resistor structures formed from gate metal and methods for fabricating such integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate with a resistor area and a transistor area. The method deposits a gate metal over the resistor area and the transistor area of the semiconductor substrate, and the gate metal forms a gate metal layer in the resistor area. The method includes etching the gate metal to form a resistor structure from the gate metal layer in the resistor area. Further, the method includes forming contacts to the resistor structure in the resistor area.Type: GrantFiled: April 24, 2014Date of Patent: December 27, 2016Assignee: GLOBALFOUNDRIES, INC.Inventors: Alexandru Romanescu, Gerd Zschätzsch, Christian Schippel -
Patent number: 9524962Abstract: A method of forming a semiconductor device including the steps of forming an electrically programmable fuse (e-fuse) on an isolation region and a transistor on an active region of a wafer, wherein forming the transistor includes forming a dummy gate above a substrate, removing the dummy gate and forming a metal gate in place of the dummy gate, and forming the e-fuse includes forming a metal-containing layer above the isolation region, forming a semiconductor layer on the metal-containing layer during the process of forming the dummy gate and of the same material as the dummy gate, forming a hard mask layer on the semiconductor layer formed on the metal-containing layer, and forming contact openings in the hard mask layer and semiconductor layer during the process of removing the dummy gate.Type: GrantFiled: December 20, 2013Date of Patent: December 20, 2016Assignee: GLOBALFOUNDRIES Inc.Inventors: Andrei Sidelnicov, Andreas Kurz, Alexandru Romanescu
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Patent number: 9478671Abstract: A semiconductor structure includes a substrate and a resistor provided over the substrate. The resistor includes a first material layer, a second material layer, a first contact structure and a second contact structure. The first material layer includes at least one of a metal and a metal compound. The second material layer includes a semiconductor material. The second material layer is provided over the first material layer and includes a first sub-layer and a second sub-layer. The second sub-layer is provided over the first sub-layer. The first sub-layer and the second sub-layer are differently doped. Each of the first contact structure and the second contact structure provides an electrical connection to the second sub-layer of the second material layer.Type: GrantFiled: January 22, 2015Date of Patent: October 25, 2016Assignee: GLOBALFOUNDRIES Inc.Inventor: Alexandru Romanescu
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Publication number: 20160204065Abstract: Integrated circuits including electronic fuse structures are disclosed. In some examples, the electronic fuse structure includes a fuse part and first and second pre-heating lines positioned generally parallel to and co-planar with the fuse part, and electrically connected with the fuse part. The electronic fuse structure also includes a cathode physically and electrically connected to the first pre-heating line and an anode physically and electrically connected to the second pre-heating line.Type: ApplicationFiled: March 22, 2016Publication date: July 14, 2016Inventors: Ricardo Mikalo, Andreas Kurz, Alexandru Romanescu
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Patent number: 9324654Abstract: Integrated circuits including electronic fuse structures are disclosed. In some examples, the electronic fuse structure includes a fuse part and first and second pre-heating lines positioned generally parallel to and co-planar with the fuse part, and electrically connected with the fuse part. The electronic fuse structure also includes a cathode physically and electrically connected to the first pre-heating line and an anode physically and electrically connected to the second pre-heating line.Type: GrantFiled: August 14, 2014Date of Patent: April 26, 2016Assignee: GLOBALFOUNDRIES, INC.Inventors: Ricardo Mikalo, Andreas Kurz, Alexandru Romanescu
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Publication number: 20160049366Abstract: Integrated circuits including electronic fuse structures are disclosed. In some examples, the electronic fuse structure includes a fuse part and first and second pre-heating lines positioned generally parallel to and co-planar with the fuse part, and electrically connected with the fuse part. The electronic fuse structure also includes a cathode physically and electrically connected to the first pre-heating line and an anode physically and electrically connected to the second pre-heating line.Type: ApplicationFiled: August 14, 2014Publication date: February 18, 2016Inventors: Ricardo Mikalo, Andreas Kurz, Alexandru Romanescu
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INTEGRATED CIRCUITS WITH RESISTOR STRUCTURES FORMED FROM GATE METAL AND METHODS FOR FABRICATING SAME
Publication number: 20150311272Abstract: Integrated circuits having resistor structures formed from gate metal and methods for fabricating such integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate with a resistor area and a transistor area. The method deposits a gate metal over the resistor area and the transistor area of the semiconductor substrate, and the gate metal forms a gate metal layer in the resistor area. The method includes etching the gate metal to form a resistor structure from the gate metal layer in the resistor area. Further, the method includes forming contacts to the resistor structure in the resistor area.Type: ApplicationFiled: April 24, 2014Publication date: October 29, 2015Applicant: GLOBALFOUNDRIES, Inc.Inventors: Alexandru Romanescu, Gerd Zschätzsch, Christian Schippel -
Publication number: 20150179632Abstract: A method of forming a semiconductor device including the steps of forming an electrically programmable fuse (e-fuse) on an isolation region and a transistor on an active region of a wafer, wherein forming the transistor includes forming a dummy gate above a substrate, removing the dummy gate and forming a metal gate in place of the dummy gate, and forming the e-fuse includes forming a metal-containing layer above the isolation region, forming a semiconductor layer on the metal-containing layer during the process of forming the dummy gate and of the same material as the dummy gate, forming a hard mask layer on the semiconductor layer formed on the metal-containing layer, and forming contact openings in the hard mask layer and semiconductor layer during the process of removing the dummy gate.Type: ApplicationFiled: December 20, 2013Publication date: June 25, 2015Applicant: GLOBALFOUNDRIES Inc.Inventors: Andrei Sidelnicov, Andreas Kurz, Alexandru Romanescu
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Publication number: 20150137316Abstract: A semiconductor structure includes a substrate and a resistor provided over the substrate. The resistor includes a first material layer, a second material layer, a first contact structure and a second contact structure. The first material layer includes at least one of a metal and a metal compound. The second material layer includes a semiconductor material. The second material layer is provided over the first material layer and includes a first sub-layer and a second sub-layer. The second sub-layer is provided over the first sub-layer. The first sub-layer and the second sub-layer are differently doped. Each of the first contact structure and the second contact structure provides an electrical connection to the second sub-layer of the second material layer.Type: ApplicationFiled: January 22, 2015Publication date: May 21, 2015Inventor: Alexandru Romanescu
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Patent number: 9012313Abstract: A semiconductor structure includes a substrate and a resistor provided over the substrate. The resistor includes a first material layer, a second material layer, a first contact structure and a second contact structure. The first material layer includes at least one of a metal and a metal compound. The second material layer includes a semiconductor material. The second material layer is provided over the first material layer and includes a first sub-layer and a second sub-layer. The second sub-layer is provided over the first sub-layer. The first sub-layer and the second sub-layer are differently doped. Each of the first contact structure and the second contact structure provides an electrical connection to the second sub-layer of the second material layer.Type: GrantFiled: February 6, 2014Date of Patent: April 21, 2015Assignee: GLOBALFOUNDRIES Inc.Inventor: Alexandru Romanescu
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Publication number: 20140264342Abstract: A semiconductor structure includes a substrate and a resistor provided over the substrate. The resistor includes a first material layer, a second material layer, a first contact structure and a second contact structure. The first material layer includes at least one of a metal and a metal compound. The second material layer includes a semiconductor material. The second material layer is provided over the first material layer and includes a first sub-layer and a second sub-layer. The second sub-layer is provided over the first sub-layer. The first sub-layer and the second sub-layer are differently doped. Each of the first contact structure and the second contact structure provides an electrical connection to the second sub-layer of the second material layer.Type: ApplicationFiled: February 6, 2014Publication date: September 18, 2014Applicant: Globalfoundries Inc.Inventor: Alexandru Romanescu