Abstract: A die seal ring including a two-dimensional electron gas is presented herein. A semiconductor device comprises an active device region. The active device region comprises a device terminal; and a die seal ring comprising a two dimensional electron gas region surrounds the active device region. By electrically coupling the device terminal to the two dimensional electron gas region, voltages at the semiconductor sidewall may be controlled to substantially equal that of the device terminal.

Abstract: A superjunction device comprising a drain contact, a substrate layer above the drain contact, an epitaxial layer above the substrate layer, a P+ layer above the epitaxial layer formed by P-type implantation to a bottom of the superjunction device, a trench with a sloped angle formed by use of a hard mask layer. The trench is filled with an insulating material. A first vertical column is formed adjacent to the trench. A second vertical column is formed adjacent to the first vertical column. A source contact is coupled to the first vertical column and the second vertical column. A P-body region is coupled to the source contact. A gate oxide is formed above the source contact and the epitaxial layer, and a gate formed above the gate oxide.

Abstract: A superjunction device comprising a drain contact, a substrate layer above the drain contact, an epitaxial layer above the substrate layer, a P+ layer above the epitaxial layer formed by P-type implantation to a bottom of the superjunction device, a trench with a sloped angle formed by use of a hard mask layer. The trench is filled with an insulating material. A first vertical column is formed adjacent to the trench. A second vertical column is formed adjacent to the first vertical column. A source contact is coupled to the first vertical column and the second vertical column. A P-body region is coupled to the source contact. A gate oxide is formed above the source contact and the epitaxial layer, and a gate formed above the gate oxide.

Abstract: A diode includes upper and lower electrodes and first and second N-type doped semiconductor substrate portions connected to the lower electrode. A first vertical transistor and a second transistor are formed in the first portion and series-connected between the electrodes. The gate of the first transistor is N-type doped and coupled to the upper electrode. The second transistor has a P channel and has a P-type doped gate. First and second doped areas of the second conductivity type are located in the second portion and are separated by a substrate portion topped with another N-type doped gate. The first doped area is coupled to the gate of the second transistor. The second doped area and the other gate are coupled to the upper electrode.

Abstract: A vertical power transistor device includes a semiconductor layer of a first conductivity type, with a plurality of dielectric regions disposed in the semiconductor layer. The dielectric regions extend in a vertical direction from a top surface of the semiconductor layer downward. Each dielectric region has a rounded-square cross-section in a horizontal plane perpendicular to the vertical direction. Adjacent ones of the dielectric regions are laterally separated by a narrow region of the semiconductor layer. Each dielectric region has a cylindrical field plate member centrally disposed therein. The cylindrical field plate member extends in the vertical direction from the top surface downward to near a bottom of the dielectric region. The dielectric region laterally separates the cylindrical field plate member from the narrow region. A source region is disposed at the top surface, and a drain region is disposed at the bottom, of the semiconductor layer.

Abstract: A vertical power transistor device includes a semiconductor layer of a first conductivity type, with a plurality of dielectric regions disposed in the semiconductor layer. The dielectric regions extend in a vertical direction from a top surface of the semiconductor layer downward. Each dielectric region has a rounded-square cross-section in a horizontal plane perpendicular to the vertical direction. Adjacent ones of the dielectric regions are laterally separated by a narrow region of the semiconductor layer. Each dielectric region has a cylindrical field plate member centrally disposed therein. The cylindrical field plate member extends in the vertical direction from the top surface downward to near a bottom of the dielectric region. The dielectric region laterally separates the cylindrical field plate member from the narrow region. A source region is disposed at the top surface, and a drain region is disposed at the bottom, of the semiconductor layer.

Abstract: A diode includes upper and lower electrodes and first and second N-type doped semiconductor substrate portions connected to the lower electrode. A first vertical transistor and a second transistor are formed in the first portion and series-connected between the electrodes. The gate of the first transistor is N-type doped and coupled to the upper electrode. The second transistor has a P channel and has a P-type doped gate. First and second doped areas of the second conductivity type are located in the second portion and are separated by a substrate portion topped with another N-type doped gate. The first doped area is coupled to the gate of the second transistor. The second doped area and the other gate are coupled to the upper electrode.

Abstract: A diode includes upper and lower electrodes and first and second N-type doped semiconductor substrate portions connected to the lower electrode. A first vertical transistor and a second transistor are formed in the first portion and series-connected between the electrodes. The gate of the first transistor is N-type doped and coupled to the upper electrode. The second transistor has a P channel and has a P-type doped gate. First and second doped areas of the second conductivity type are located in the second portion and are separated by a substrate portion topped with another N-type doped gate. The first doped area is coupled to the gate of the second transistor. The second doped area and the other gate are coupled to the upper electrode.

Abstract: A vertical power transistor device includes a semiconductor layer of a first conductivity type, with a plurality of dielectric regions disposed in the semiconductor layer. The dielectric regions extend in a vertical direction from a top surface of the semiconductor layer downward. Each dielectric region has a rounded-square cross-section in a horizontal plane perpendicular to the vertical direction. Adjacent ones of the dielectric regions are laterally separated by a narrow region of the semiconductor layer. Each dielectric region has a cylindrical field plate member centrally disposed therein. The cylindrical field plate member extends in the vertical direction from the top surface downward to near a bottom of the dielectric region. The dielectric region laterally separates the cylindrical field plate member from the narrow region. A source region is disposed at the top surface, and a drain region is disposed at the bottom, of the semiconductor layer.

Abstract: A semiconductor device including a dummy pillar and a plurality of racetrack pillars. The dummy pillar of semiconductor material extends in a first lateral direction. The plurality of racetrack pillars, including the semiconducting material, surrounds the dummy pillar. Each of the plurality of racetrack pillars has a first linear section, which extends in the first lateral direction, and a first rounded section to form a racetrack shape. The plurality of racetrack pillars includes a first racetrack pillar and a second racetrack pillar. The first racetrack pillar is disposed proximate to the dummy pillar and the second racetrack pillar surrounds the first racetrack pillar. The first racetrack pillar is disposed between the dummy pillar and the second racetrack pillar. The semiconductor device includes a plurality of spacing regions including a first spacing region that surrounds the dummy pillar and is disposed between the first racetrack pillar and the dummy pillar.

Abstract: A vertical power transistor device includes a semiconductor layer of a first conductivity type, with a plurality of dielectric regions disposed in the semiconductor layer. The dielectric regions extend in a vertical direction from a top surface of the semiconductor layer downward. Each dielectric region has a rounded-square cross-section in a horizontal plane perpendicular to the vertical direction. Adjacent ones of the dielectric regions are laterally separated by a narrow region of the semiconductor layer. Each dielectric region has a cylindrical field plate member centrally disposed therein. The cylindrical field plate member extends in the vertical direction from the top surface downward to near a bottom of the dielectric region. The dielectric region laterally separates the cylindrical field plate member from the narrow region. A source region is disposed at the top surface, and a drain region is disposed at the bottom, of the semiconductor layer.

Abstract: A semiconductor device including a dummy pillar and a plurality of racetrack pillars. The dummy pillar of semiconductor material extends in a first lateral direction. The plurality of racetrack pillars, including the semiconducting material, surrounds the dummy pillar. Each of the plurality of racetrack pillars has a first linear section, which extends in the first lateral direction, and a first rounded section to form a racetrack shape. The plurality of racetrack pillars includes a first racetrack pillar and a second racetrack pillar. The first racetrack pillar is disposed proximate to the dummy pillar and the second racetrack pillar surrounds the first racetrack pillar. The first racetrack pillar is disposed between the dummy pillar and the second racetrack pillar. The semiconductor device includes a plurality of spacing regions including a first spacing region that surrounds the dummy pillar and is disposed between the first racetrack pillar and the dummy pillar.

Abstract: A diode includes upper and lower electrodes and first and second N-type doped semiconductor substrate portions connected to the lower electrode. A first vertical transistor and a second transistor are formed in the first portion and series-connected between the electrodes. The gate of the first transistor is N-type doped and coupled to the upper electrode. The second transistor has a P channel and has a P-type doped gate. First and second doped areas of the second conductivity type are located in the second portion and are separated by a substrate portion topped with another N-type doped gate. The first doped area is coupled to the gate of the second transistor. The second doped area and the other gate are coupled to the upper electrode.

Abstract: Diodes and methods of manufacturing diodes are disclosed. In some examples, the diodes may include a cathode assembly. The cathode assembly may include a cathode electrode and a N+ substrate layer on the cathode electrode. The cathode assembly may additionally include a N buffer layer on the N+ substrate layer, and a N? bulk layer on the N buffer layer. The N buffer layer may be disposed between the N+ substrate layer and the N? bulk layer. Additionally, the N buffer layer may include at least one damaged sublayer having crystal damage configured to provide recombination centers for charge carriers and at least one undamaged sublayer that excludes crystal damage. The diodes may additionally include an anode assembly adjacent to the N? bulk layer.

Abstract: Diodes and methods of manufacturing diodes are disclosed. In some examples, the diodes may include a cathode assembly. The cathode assembly may include a cathode electrode and a N+ substrate layer on the cathode electrode. The cathode assembly may additionally include a N buffer layer on the N+ substrate layer, and a N? bulk layer on the N buffer layer. The N buffer layer may be disposed between the N+ substrate layer and the N? bulk layer. Additionally, the N buffer layer may include at least one damaged sublayer having crystal damage configured to provide recombination centers for charge carriers and at least one undamaged sublayer that excludes crystal damage. The diodes may additionally include an anode assembly adjacent to the N? bulk layer.

Abstract: Diodes and methods of manufacturing diodes are disclosed. The diodes may include a cathode assembly and an anode assembly having an anode electrode, a gate electrode layer under the anode electrode, a gate oxide layer under the gate electrode layer, at least one P? body region under the gate oxide layer, and at least one trench that extends through the gate electrode layer, the gate oxide layer, and the at least one P? body region to the cathode assembly. The at least one trench may include a lower portion having (1) a bottom and a plurality of sidewalls defining a bottom volume and having an insulating layer and (2) a conductive material that is disposed within the bottom volume and that is in electrical communication with the anode electrode. The anode electrode may contact extend through the at least one trench to the conductive material.

Abstract: Diodes and methods of manufacturing diodes are disclosed. The diodes may include a cathode assembly having a cathode electrode, a N+ substrate layer on the cathode electrode, a N buffer layer on the N+ substrate layer, and a N? bulk layer on the N buffer layer. The N buffer layer may include crystal damage configured to provide recombination centers for charge carriers. The method may include creating a N buffer layer on a N+ substrate wafer, creating a N? bulk layer on the N buffer layer, and inflicting, to the N buffer layer, crystal damage configured to provide recombination centers for charge carriers. The method may include creating a N buffer layer in a N? bulk wafer, creating a N+ substrate layer in the N? bulk wafer, and inflicting, to the N buffer layer, crystal damage configured to provide recombination centers for charge carriers.

Abstract: Diodes and methods of manufacturing diodes are disclosed. The diodes may include a cathode assembly having a cathode electrode, a N+ substrate layer on the cathode electrode, a N buffer layer on the N+ substrate layer, and a N? bulk layer on the N buffer layer. The N buffer layer may include crystal damage configured to provide recombination centers for charge carriers. The method may include creating a N buffer layer on a N+ substrate wafer, creating a N? bulk layer on the N buffer layer, and inflicting, to the N buffer layer, crystal damage configured to provide recombination centers for charge carriers. The method may include creating a N buffer layer in a N? bulk wafer, creating a N+ substrate layer in the N? bulk wafer, and inflicting, to the N buffer layer, crystal damage configured to provide recombination centers for charge carriers.

Abstract: Diodes and methods of manufacturing diodes are disclosed. The diodes may include a cathode assembly and an anode assembly having an anode electrode, a gate electrode layer under the anode electrode, a gate oxide layer under the gate electrode layer, at least one P? body region under the gate oxide layer, and at least one trench that extends through the gate electrode layer, the gate oxide layer, and the at least one P? body region to the cathode assembly. The at least one trench may include a lower portion having (1) a bottom and a plurality of sidewalls defining a bottom volume and having an insulating layer and (2) a conductive material that is disposed within the bottom volume and that is in electrical communication with the anode electrode. The anode electrode may contact extend through the at least one trench to the conductive material.

Abstract: A rectifier building block has four electrodes: source, drain, gate and probe. The main current flows between the source and drain electrodes. The gate voltage controls the conductivity of a narrow channel under a MOS gate and can switch the RBB between OFF and ON states. Used in pairs, the RBB can be configured as a three terminal half-bridge rectifier which exhibits better than ideal diode performance, similar to synchronous rectifiers but without the need for control circuits. N-type and P-type pairs can be configured as a full bridge rectifier. Other combinations are possible to create a variety of devices.