Abstract: The embodiments set forth a technique for coordinating notifications across computing devices placed onto a wireless charging apparatus. According to some embodiments, the technique can involve the wireless charging apparatus (1) receiving, from a first computing device, first information that includes (i) a first unique identifier (ID) associated with the first computing device, and (ii) one or more unique IDs that are each associated with a respective auxiliary computing device known to the first computing device. Subsequently, the wireless charging apparatus can receive, from a second computing device, second information that at least includes a second unique ID associated with the second computing device. Finally, the wireless charging apparatus can, in response to determining that the second unique ID is included in the one or more unique IDs, and cause both the first and second computing devices to display respective notifications in a coordinated manner.

Abstract: A wireless power system includes a wireless power transmitting device such as a wireless charging mat for charging devices such as a cellular telephone and an earbuds battery case. The earbuds battery case receives earbuds and charges the earbuds from a battery. The wireless charging mat supports bidirectional in-band communications between the cellular telephone and the earbuds battery case. The earbuds battery case provides the cellular telephone with information on the battery charge level associated with the battery in the earbuds battery case and a battery charge level associated with each earbud in the earbuds battery case. The cellular telephone receives battery charge level information through the wireless charging mat and displays corresponding indicators. The earbuds battery case has a visual output device such as a light-emitting diode that is illuminated to indicate that the earbuds battery case is being charged.

Abstract: The embodiments set forth a technique for coordinating notifications across computing devices placed onto a wireless charging apparatus. According to some embodiments, the technique can involve the wireless charging apparatus (1) receiving, from a first computing device, first information that includes (i) a first unique identifier (ID) associated with the first computing device, and (ii) one or more unique IDs that are each associated with a respective auxiliary computing device known to the first computing device. Subsequently, the wireless charging apparatus can receive, from a second computing device, second information that at least includes a second unique ID associated with the second computing device. Finally, the wireless charging apparatus can, in response to determining that the second unique ID is included in the one or more unique IDs, and cause both the first and second computing devices to display respective notifications in a coordinated manner.

Abstract: A wireless charging system may include a wireless power transmitting device that receives multiple wireless power receiving devices. A primary power receiving device that is used to display battery charge status information for other power receiving devices on the power transmitting device may be referred to as a hero device. The other wireless power receiving devices may be referred to as paired devices. When a paired device is added to a wireless power transmitting device where a hero device is already present, the hero device may verify that the paired device is on the same mat as the hero device. The hero device and paired device may then synchronously output a user notification. When a paired device is present on a wireless power transmitting device, the paired device may send battery charge status information to the wireless power transmitting device at predetermined intervals.

Abstract: In an embodiment, a system on a chip (SOC) may include one or more central processing units (CPUs), a memory controller, and a circuit configured to remain powered on when the rest of the SOC is powered down. The circuit may be configured to receive audio samples and match those audio samples against a predetermined pattern. The circuit may operate according to a first clock during the time that the rest of the SOC is powered down. In response to detecting the predetermined pattern in the samples, the circuit may cause the memory controller and processors to power up. During the power up process, a second clock having one or more better characteristics than the first clock may become available. The circuit may switch to the second clock while preserving the samples, or losing at most one sample, or no more than a threshold number of samples.

Abstract: In an embodiment, a system on a chip (SOC) may include one or more central processing units (CPUs), a memory controller, and a circuit configured to remain powered on when the rest of the SOC is powered down. The circuit may be configured to receive audio samples and match those audio samples against a predetermined pattern. The circuit may operate according to a first clock during the time that the rest of the SOC is powered down. In response to detecting the predetermined pattern in the samples, the circuit may cause the memory controller and processors to power up. During the power up process, a second clock having one or more better characteristics than the first clock may become available. The circuit may switch to the second clock while preserving the samples, or losing at most one sample, or no more than a threshold number of samples.

Abstract: In an embodiment, a system on a chip (SOC) may include one or more central processing units (CPUs), a memory controller, and a circuit configured to remain powered on when the rest of the SOC is powered down. The circuit may be configured to receive audio samples and match those audio samples against a predetermined pattern. The circuit may operate according to a first clock during the time that the rest of the SOC is powered down. In response to detecting the predetermined pattern in the samples, the circuit may cause the memory controller and processors to power up. During the power up process, a second clock having one or more better characteristics than the first clock may become available. The circuit may switch to the second clock while preserving the samples, or losing at most one sample, or no more than a threshold number of samples.

Abstract: Interface circuits that may utilize a limited number of pins to detect a presence of an accessory, determine whether the accessory can provide or receive power, communicate with the accessory regarding at least that transfer of power, and transfer power accordingly. One example may provide detection circuitry for a host that may detect the presence of a pull-down resistor on a data pin of an accessory. The pull-down may indicate that a power consuming accessory has been connected. This example may detect the presence of power on a power pin. The presence of the power on the power pin may indicate that a power providing accessory has been connected.

Abstract: Methods, circuits, and apparatus to distribute power among devices in an electronic system where a device may receive power from more than one source, may have a bidirectional power connector, or both. One example may resolve conflicts when an electronic device receives power from more than one source. In this example, the device may determine which source may provide the most power, and may select to receive power from the power source that may deliver the most power. Other examples may have a preference to receive power from a particular source or via a specific connector. Other examples may switch from receiving power over a first connector to providing power over the first connector, while others may receive and provide power over different connectors at the same time. Another may be connected to a battery, and may draw power from the battery or not depending on the type of battery.

Abstract: In an embodiment, a system on a chip (SOC) may include one or more central processing units (CPUs), a memory controller, and a circuit configured to remain powered on when the rest of the SOC is powered down. The circuit may be configured to receive audio samples and match those audio samples against a predetermined pattern. The circuit may operate according to a first clock during the time that the rest of the SOC is powered down. In response to detecting the predetermined pattern in the samples, the circuit may cause the memory controller and processors to power up. During the power up process, a second clock having one or more better characteristics than the first clock may become available. The circuit may switch to the second clock while preserving the samples, or losing at most one sample, or no more than a threshold number of samples.

Abstract: Due to software bugs, hardware bugs, power fluctuations, cosmic rays, and various other causes, computing systems may from time to time enter various types of error states. This disclosure relates generally to the field of watchdog timers configured to take corrective action when a computing system enters such an error state. In various embodiments, this disclosure provides systems, methods, apparatuses, and computer-readable media for multi-tier watchdog timers. Such multi-tier watchdog timers may be configured to take different levels of corrective action at different times and/or under different conditions.