Patents by Inventor Alexei Ioudovsky
Alexei Ioudovsky has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250148185Abstract: Described are various embodiments of a system and method for automatic extraction of integrated circuit component data. In one embodiment, a method is provided for automatically extracting transistor data from a digital representation of an integrated circuit that comprises digitally defining at least one diffusion space corresponding to a respective spatial region of the IC that comprises at least one diffusion feature. For each discrete diffusion space, diffusion space circuit features that intersect with each diffusion feature are incrementally assessed by assigning a current state value to each diffusion space circuit feature based on an identified feature characteristic associated therewith and an identified feature characteristic of an electrically adjacent feature in the diffusion space.Type: ApplicationFiled: February 9, 2023Publication date: May 8, 2025Inventors: Christopher PAWLOWICZ, Michael GREEN, Alexei IOUDOVSKI, Bruno MACHADO TRINDADE
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Patent number: 8855386Abstract: A method for performing registration of multispectral retinal images. Corresponding cross-over points and bifurcation points of blood vessel in an eye are identified in a fixed image and in an offset image. The relative displacement of each point, between the images, is calculated. Based on these relative displacements, the offset of each pixel in the offset image is interpolated and the offset image is transformed into a corrected (distorted) image. Such an image can be used to assess the health of the eye. Further, a fixed image and a offset image of an eye are divided in a tile pattern. The relative displacement of each tile of the offset image with respect to the corresponding tile in the fixed image is calculated. An offset for each tile is calculated and the offset image is corrected as a function of those offsets.Type: GrantFiled: January 21, 2011Date of Patent: October 7, 2014Assignee: Annidis Health Systems Corp.Inventors: Alexei Ioudovski, Alan Boate
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Publication number: 20120300998Abstract: A method for performing registration of multispectral retinal images. Corresponding cross-over points and bifurcation points of blood vessel in an eye are identified in a fixed image and in an offset image. The relative displacement of each point, between the images, is calculated. Based on these relative displacements, the offset of each pixel in the offset image is interpolated and the offset image is transformed into a corrected (distorted) image. Such an image can be used to assess the health of the eye. Further, a fixed image and a offset image of an eye are divided in a tile pattern. The relative displacement of each tile of the offset image with respect to the corresponding tile in the fixed image is calculated. An offset for each tile is calculated and the offset image is corrected as a function of those offsets.Type: ApplicationFiled: January 21, 2011Publication date: November 29, 2012Applicant: ANNIDIS HEALTH SYSTEMS CORP.Inventors: Alexei Ioudovski, Alan Boate
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Patent number: 8107718Abstract: A method, system, and apparatus use in locating a structure in an integrated circuit are provided. Electrical activities are induced in the IC for producing respective unique electromagnetic radiation patterns that collectively contain information on the location of the structure. The electromagnetic radiation patterns are detected, and an area of interest for locating the structure is determined from correlations in the electromagnetic radiation patterns. Once the area of interest is identified a user can more easily locate the structure on the integrated circuit by focusing on the area of interest.Type: GrantFiled: March 14, 2007Date of Patent: January 31, 2012Assignee: Global Intellectual StrategiesInventors: Pierrette M. Breton, Alexei Ioudovski
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Patent number: 6738957Abstract: A process in a computer system for generating a high level schematic from a project schematic of basic components which comprises scanning the project schematic for a predetermined cell, wherein the cell is made up of a select group of components and their interconnections, and replacing the select group of components on every occurrence that it is found in the project schematic by a cell symbol having input and outputs to generate the high level schematic. The process may also be repeated for other predetermined cells which may be selected from a library or created by the user.Type: GrantFiled: August 3, 2001Date of Patent: May 18, 2004Assignee: Semiconductor Insights Inc.Inventors: Val Gont, Jason Abt, Larry Lam, Alexei Ioudovski
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Publication number: 20020038446Abstract: A computer process for extracting logic gates and/or functional cells from a transistor netlist. The process comprises the steps of scanning the netlist for transistor blocks of p-type and n-type transistors, determining if the p-type transistors and the n-type transistors are complementary or non-complementary and identifying the logic gate for each of the complementary transistor blocks and/or the functional cell for each of the non-complementary blocks. A transistor block is a group of p-type transistors connected through their sources and drains between a power node and a common node, and a group n-type transistors connected through their sources and drains between a ground node and the common node. Complementarity may be determined by iteratively seeking the serial connections and the parallel connections for the p-type transistors and the n-type transistors, identifying the main p-type transistor branch and the main n-type transistor branch, and comparing the branches.Type: ApplicationFiled: August 3, 2001Publication date: March 28, 2002Applicant: Gate ExtractorInventor: Alexei Ioudovski
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Publication number: 20020023107Abstract: A process in a computer system for generating a high level schematic from a project schematic of basic components which comprises scanning the project schematic for a predetermined cell, wherein the cell is made up of a select group of components and their interconnections, and replacing the select group of components on every occurrence that it is found in the project schematic by a cell symbol having input and outputs to generate the high level schematic. The process may also be repeated for other predetermined cells which may be selected from a library or created by the user.Type: ApplicationFiled: August 3, 2001Publication date: February 21, 2002Applicant: Semiconductor Insights Inc.Inventors: Val Gont, Jason Abt, Larry Lam, Alexei Ioudovski
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Patent number: 5694481Abstract: A method of analyzing at least a portion of an integrated circuit (IC) comprised of the steps of automatically: (a) scanning at least a portion of a layer of an integrated circuit using high magnification to provide first digital signals representing pixel amplitudes, (b) extracting features of interest from the first digital signals to provide second digital signals representing values of groups of pixels defining the features of interest, (c) modifying the second digital signals representing adjacent features of interest from step (b) so as to mosaic the features of interest and providing third signals representing a seamless representation of the layer, (d) repeating steps (a), (b) and (c) for other layers of the integrated circuit, whereby plural third signals representing plural ones of the layers are provided, (e) registering the plural third signals relative to each other so as to represent vertical alignment of the layers by determining features of interest representative of IC mutual interconnectionType: GrantFiled: April 12, 1995Date of Patent: December 2, 1997Assignee: Semiconductor Insights Inc.Inventors: Larry Lam, George Chamberlain, Alexei Ioudovsky, Ghassan Naim