Patents by Inventor Alexey Heiman
Alexey Heiman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11374120Abstract: For example, an Electrostatically Formed Nanowire (EFN) may include a source region; at least one drain region; a wire region configured to drive a current between the source and drain regions via a conductive channel; a first lateral-gate area extending along a first surface of the wire region between the source and drain regions; a second lateral-gate area extending along a second surface of the wire region between the source and drain regions; and a sensing area in opening in a backside of a silicon substrate under the wire region and the first and second lateral-gate areas, the sensing area configured to, in reaction to a predefined substance, cause a change in a conductivity of the conductive channel.Type: GrantFiled: May 10, 2020Date of Patent: June 28, 2022Assignees: TOWER SEMICONDUCTOR LTD., RAMOT AT TEL AVIV UNIVERSITY LTD.Inventors: Zohar Shaked, Yakov Roizin, Menachem Vofsy, Alexey Heiman, Yossi Rosenwaks, Klimentiy Shimanovich, Yhonatan Vaknin
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Patent number: 10840128Abstract: A method for manufacturing a semiconductor device, the method may include forming a first part of a hollow in first part of a first layer of the semiconductor device and coating a sidewall of the first part of the hollow with an etch stop material, wherein the forming of the first part of the hollow comprises performing at least one iteration of (i) anisotropic etching and (ii) deposition of the etch stop material; wherein when completed, the semiconductor device comprises a radio frequency (RF) circuit; forming a second part of the hollow in a second part of the first layer by performing isotropic etching that involves directing plasma through the first part of the hollow; wherein the second part of the hollow reaches either (a) a bottom of a second layer of the semiconductor device or (b) the RF circuit; and wherein at least a majority of the second part of the hollow is wider than at least a majority of the first part of the hollow.Type: GrantFiled: January 14, 2019Date of Patent: November 17, 2020Assignee: Tower Semiconductors Ltd.Inventors: Alex Sirkis, Alexey Heiman, Yakov Roizin
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Patent number: 10788375Abstract: Some demonstrative embodiments include an apparatus of a temperature sensor to sense temperature, the apparatus including a first pad on a silicon substrate; a second pad on the silicon substrate; a silicon nanowire having a first end coupled to the first pad and a second end coupled to the second pad, the silicon nanowire configured to drive a current between the first pad and the second pad, the current depending at least on the temperature; and a charged dielectric layer covering at least three sides of the silicon nanowire.Type: GrantFiled: December 7, 2017Date of Patent: September 29, 2020Assignee: TOWER SEMICONDUCTOR LTD.Inventors: Yakov Roizin, Menachem Vofsy, Alexey Heiman, Yossi Rosenwaks, Klimentiy Shimanovich, Yhonatan Vaknin
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Patent number: 10770586Abstract: A multi-layer SiN stressing stack (structure) including a thin lower SiN layer and a thick upper SiN layer is formed over NiSi silicide structures and functions to generate tensile channel stress in NMOS transistors. The lower SiN layer is formed directly on the silicided surfaces, and has a low hydrogen content and a relatively low residual stress. The upper SiN layer is then formed on the lower SiN layer using process parameters that produce a relatively high residual stress, and also cause the upper SiN material to have relatively high hydrogen content. The lower SiN layer functions as a barrier that prevents/minimizes hydrogen migration to the silicide structures, which prevents defects leading to NiSi failures. The upper SiN layer functions to generate desirable high tensile stress in the underlying NMOS channel region to enhance the mobility of channel electrons. In some embodiments other dielectric materials are used.Type: GrantFiled: February 4, 2018Date of Patent: September 8, 2020Assignee: Tower Semiconductor Ltd.Inventors: Alexey Heiman, Igor Aisenberg, Abed Qaddah, Yakov Roizin
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Patent number: 10770573Abstract: For example, an Electrostatically Formed Nanowire (EFN) may include a source region; at least one drain region; a wire region configured to drive a current between the source and drain regions via a conductive channel; a first lateral-gate area extending along a first surface of the wire region between the source and drain regions; a second lateral-gate area extending along a second surface of the wire region between the source and drain regions; and a sensing area in opening in a backside of a silicon substrate under the wire region and the first and second lateral-gate areas, the sensing area configured to, in reaction to a predefined substance, cause a change in a conductivity of the conductive channel.Type: GrantFiled: September 20, 2018Date of Patent: September 8, 2020Assignees: TOWER SEMICONDUCTOR LTD., RAMOT AT TEL AVIV UNIVERSITY LTD.Inventors: Zohar Shaked, Yakov Roizin, Menachem Vofsy, Alexey Heiman, Yossi Rosenwaks, Klimentiy Shimanovich, Yhonatan Vaknin
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Publication number: 20200273972Abstract: For example, an Electrostatically Formed Nanowire (EFN) may include a source region; at least one drain region; a wire region configured to drive a current between the source and drain regions via a conductive channel; a first lateral-gate area extending along a first surface of the wire region between the source and drain regions; a second lateral-gate area extending along a second surface of the wire region between the source and drain regions; and a sensing area in opening in a backside of a silicon substrate under the wire region and the first and second lateral-gate areas, the sensing area configured to, in reaction to a predefined substance, cause a change in a conductivity of the conductive channel.Type: ApplicationFiled: May 10, 2020Publication date: August 27, 2020Applicants: TOWER SEMICONDUCTOR LTD., RAMOT at Tel Aviv University Ltd.Inventors: Zohar Shaked, Yakov Roizin, Menachem Vofsy, Alexey Heiman, Yossi Rosenwaks, Klimentiy Shimanovich, Yhonatan Vaknin
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Publication number: 20200227309Abstract: A method for manufacturing a semiconductor device, the method may include forming a first part of a hollow in first part of a first layer of the semiconductor device and coating a sidewall of the first part of the hollow with an etch stop material, wherein the forming of the first part of the hollow comprises performing at least one iteration of (i) anisotropic etching and (ii) deposition of the etch stop material; wherein when completed, the semiconductor device comprises a radio frequency (RF) circuit; forming a second part of the hollow in a second part of the first layer by performing isotropic etching that involves directing plasma through the first part of the hollow; wherein the second part of the hollow reaches either (a) a bottom of a second layer of the semiconductor device or (b) the RF circuit; and wherein at least a majority of the second part of the hollow is wider than at least a majority of the first part of the hollow.Type: ApplicationFiled: January 14, 2019Publication date: July 16, 2020Inventors: Alex Sirkis, Alexey Heiman, Yakov Roizin
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Patent number: 10707120Abstract: An RF SOI device combines a triple-layer stressing stack and patterned low-k features (i.e., low-k polymer structures and/or air gap regions) disposed in pre-metal dielectric over the gate structures of NMOS transistors. The triple-layer stressing stack includes a thick SiN or oxynitride lower stressor layer that applies tensile stress in the channel regions of the NMOS transistors, a thin intermediate buffer layer, an upper etch-stop layer. After Metal-1 processing is completed, a special etching process is performed to define air gaps in the pre-metal dielectric over the NMOS gate structures using upper layer(s) of the triple-layer stressing stack as an etch stop to prevent damage to the stressor layer. A non-conformal dielectric material or an optional low-k dielectric material is then deposited in or over the air gaps to complete formation of the low-k features, and an optional capping or sealing layer is formed over the completed low-k features.Type: GrantFiled: April 3, 2019Date of Patent: July 7, 2020Assignee: Tower Semiconductor Ltd.Inventors: Bouhnik Yami, Nagar Magi, Barhum Liat, Alexey Heiman, Yakov Roizin
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Publication number: 20200098906Abstract: For example, an Electrostatically Formed Nanowire (EFN) may include a source region; at least one drain region; a wire region configured to drive a current between the source and drain regions via a conductive channel; a first lateral-gate area extending along a first surface of the wire region between the source and drain regions; a second lateral-gate area extending along a second surface of the wire region between the source and drain regions; and a sensing area in opening in a backside of a silicon substrate under the wire region and the first and second lateral-gate areas, the sensing area configured to, in reaction to a predefined substance, cause a change in a conductivity of the conductive channel.Type: ApplicationFiled: September 20, 2018Publication date: March 26, 2020Inventors: Zohar Shaked, Yakov Roizin, Menachem Vofsy, Alexey Heiman, Yossi Rosenwaks, Klimentiy Shimanovich, Yhonatan Vaknin
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Publication number: 20190245086Abstract: A multi-layer SiN stressing stack (structure) including a thin lower SiN layer and a thick upper SiN layer is formed over NiSi silicide structures and functions to generate tensile channel stress in NMOS transistors. The lower SiN layer is formed directly on the silicided surfaces, and has a low hydrogen content and a relatively low residual stress. The upper SiN layer is then formed on the lower SiN layer using process parameters that produce a relatively high residual stress, and also cause the upper SiN material to have relatively high hydrogen content. The lower SiN layer functions as a barrier that prevents/minimizes hydrogen migration to the silicide structures, which prevents defects leading to NiSi failures. The upper SiN layer functions to generate desirable high tensile stress in the underlying NMOS channel region to enhance the mobility of channel electrons. In some embodiments other dielectric materials are used.Type: ApplicationFiled: February 4, 2018Publication date: August 8, 2019Inventors: Alexey Heiman, Igor Aisenberg, Abed Qaddah, Yakov Roizin
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Publication number: 20190178725Abstract: Some demonstrative embodiments include an apparatus of a temperature sensor to sense temperature, the apparatus including a first pad on a silicon substrate; a second pad on the silicon substrate; a silicon nanowire having a first end coupled to the first pad and a second end coupled to the second pad, the silicon nanowire configured to drive a current between the first pad and the second pad, the current depending at least on the temperature; and a charged dielectric layer covering at least three sides of the silicon nanowire.Type: ApplicationFiled: December 7, 2017Publication date: June 13, 2019Inventors: Yakov Roizin, Menachem Vofsy, Alexey Heiman, Yossi Rosenwaks, Klimentiy Shimanovich, Yhonatan Vaknin
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Patent number: 9837411Abstract: A semiconductor die that may include a substrate; an epitaxial layer; a metal layer; a first transistor; and a metal via that surrounds the first transistor, extends between the metal layer and the substrate, and penetrates the substrate.Type: GrantFiled: July 14, 2015Date of Patent: December 5, 2017Assignee: TOWER SEMICONDUCTORS LTD.Inventors: Sharon Levin, Alexey Heiman, Sagy Levy
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Publication number: 20170018503Abstract: A semiconductor die that may include a substrate; an epitaxial layer; a metal layer; a first transistor; and a metal via that surrounds the first transistor, extends between the metal layer and the substrate, and penetrates the substrate.Type: ApplicationFiled: July 14, 2015Publication date: January 19, 2017Inventors: Sharon Levin, Alexey Heiman, Sagy Levy
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Patent number: 9330979Abstract: A low Rdson LDMOS transistor having a shallow field oxide region that separates a gate electrode of the transistor from a drain diffusion region of the transistor. The shallow field oxide region is formed separate from the field isolation regions (e.g., STI regions) used to isolate circuit elements on the substrate. Fabrication of the shallow field oxide region is controlled such that this region extends below the upper surface of the semiconductor substrate to a depth that is much shallower than the depth of field isolation regions. For example, the shallow field oxide region may extend below the upper surface of the substrate by only Angstroms or less. As a result, the current path through the resulting LDMOS transistor is substantially unimpeded by the shallow field oxide region, resulting in a low on-resistance.Type: GrantFiled: October 29, 2008Date of Patent: May 3, 2016Assignee: Tower Semiconductor Ltd.Inventors: Sharon Levin, Alexey Heiman, Zohar Shaked, Gal Fleishon
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Patent number: 8722484Abstract: A method for improving the reliability of a high-k dielectric layer or a high-k dielectric stack by forming an amorphous high-k dielectric layer over an insulating layer, doping the amorphous high-k dielectric layer with nitrogen atoms, and subsequently heating the resulting structure at a temperature greater than or equal to the crystallization temperature of the high-k dielectric material, thereby transforming the high-k dielectric material from an amorphous state to a crystalline state, and causing nitrogen atoms to diffuse into the insulating layer.Type: GrantFiled: January 14, 2008Date of Patent: May 13, 2014Assignee: Tower Semiconductor Ltd.Inventors: Michael Lisiansky, Yakov Roizin, Alexey Heiman, Amos Fenigstein
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Patent number: 8722496Abstract: A cost-efficient SONOS (CEONOS) non-volatile memory (NVM) cell production method for CMOS ICs, where the CEONOS NVM cell requires two or three additional masks, but can otherwise be formed using the same standard CMOS flow processes used to form NMOS transistors. A first additional mask is used to form an oxide-nitride-oxide (ONO) layer that replaces the standard NMOS gate oxide and serves to store NVM data (i.e., trapped charges). A second additional mask is used to perform drain engineering, including a special pocket implant and LDD extensions, which facilitates program/erase of the CEONOS NVM cells using low voltages (e.g., 5V). The polysilicon gate, source/drain contacts and metallization are formed using corresponding NMOS processes. The CEONOS NVM cells are arranged in a space-efficient X-array pattern such that each group of four cells share three bit lines. Programming involves standard CHE injection or pulse agitated interface substrate hot electron injection (PAISHEI).Type: GrantFiled: January 31, 2013Date of Patent: May 13, 2014Assignee: Tower Semiconductor Ltd.Inventors: Yakov Roizin, Evgeny Pikhay, Alexey Heiman, Micha Gutman
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Patent number: 8501573Abstract: An X-ray image sensor having scintillating material embedded into wave-guide structures fabricated in a CMOS image sensor (CIS). After the CIS has been fabricated, openings (deep pores) are formed in the back side of the CIS wafer. These openings terminate at a distance of about 1 to 5 microns below the upper silicon surface of the wafer. The depth of these openings can be controlled by stopping on a buried insulating layer, or by stopping on an epitaxial silicon layer having a distinctive doping concentration. The openings are aligned with corresponding photodiodes of the CIS. The openings may have a shape that narrows as approaching the photodiodes. A thin layer of a reflective material may be formed on the sidewalls of the openings, thereby improving the efficiency of the resulting waveguide structures. Scintillating material (e.g., CsI(Tl)) is introduced into the openings using a ForceFillâ„¢ technology or by mechanical pressing.Type: GrantFiled: February 20, 2009Date of Patent: August 6, 2013Assignee: Tower Semiconductor Ltd.Inventors: Yakov Roizin, Amos Fenigstein, Avi Strum, Alexey Heiman, Doron Pardess
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Patent number: 7754559Abstract: A capacitor structure is fabricated with only slight modifications to a conventional single-poly CMOS process. After front-end processing is completed, grooves are etched through the pre-metal dielectric layer to expose polysilicon structures, which may be salicided or non-salicided. A dielectric layer is formed over the exposed polysilicon structures. A conventional contact process module is then used to form contact openings through the pre-metal dielectric layer. The mask used to form the contact openings is then removed, and conventional contact metal deposition steps are performed, thereby simultaneously filling the contact openings and the grooves with the contact (electrode) metal stack. A planarization step removes the upper portion of the metal stack, thereby leaving metal contacts in the contact openings, and metal electrodes in the grooves. The metal electrodes may form, for example, transistor gates, EEPROM control gates or capacitor plates.Type: GrantFiled: March 19, 2008Date of Patent: July 13, 2010Assignee: Tower Semiconductor Ltd.Inventors: Efraim Aloni, Yakov Roizin, Alexey Heiman, Michael Lisiansky, Amos Fenigstein, Myriam Buchbinder
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Publication number: 20100102388Abstract: A low Rdson LDMOS transistor having a shallow field oxide region that separates a gate electrode of the transistor from a drain diffusion region of the transistor. The shallow field oxide region is formed separate from the field isolation regions (e.g., STI regions) used to isolate circuit elements on the substrate. Fabrication of the shallow field oxide region is controlled such that this region extends below the upper surface of the semiconductor substrate to a depth that is much shallower than the depth of field isolation regions. For example, the shallow field oxide region may extend below the upper surface of the substrate by only Angstroms or less. As a result, the current path through the resulting LDMOS transistor is substantially unimpeded by the shallow field oxide region, resulting in a low on-resistance.Type: ApplicationFiled: October 29, 2008Publication date: April 29, 2010Applicant: Tower Semiconductor Ltd.Inventors: Sharon Levin, Alexey Heiman, Zohar Kuritsky, Gal Fleishon
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Publication number: 20090181530Abstract: A method for improving the reliability of a high-k dielectric layer or a high-k dielectric stack by forming an amorphous high-k dielectric layer over an insulating layer, doping the amorphous high-k dielectric layer with nitrogen atoms, and subsequently heating the resulting structure at a temperature greater than or equal to the crystallization temperature of the high-k dielectric material, thereby transforming the high-k dielectric material from an amorphous state to a crystalline state, and causing nitrogen atoms to diffuse into the insulating layer.Type: ApplicationFiled: January 14, 2008Publication date: July 16, 2009Applicant: Tower Semiconductor Ltd.Inventors: Michael Lisiansky, Yakov Roizin, Alexey Heiman, Amos Fenigstein