Patents by Inventor Alexey Kudymov
Alexey Kudymov has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240030337Abstract: An HFET includes a first and second semiconductor material. A first composite passivation layer includes a first insulation layer and a first passivation layer, and the first passivation layer is disposed between the first insulation layer and the second semiconductor material. The HFET includes a second passivation layer, where the first insulation layer is disposed between the first passivation layer and the second passivation layer. A gate dielectric is disposed between the second semiconductor material and the first passivation layer. A source electrode and a drain electrode are coupled to the second semiconductor material, and a gate electrode is disposed laterally between the source electrode and the drain electrode. A first gate field plate is disposed between the first passivation layer and the second passivation layer and electrically connected to the gate electrode, and a second gate field plate is disposed above first gate field plate.Type: ApplicationFiled: June 20, 2023Publication date: January 25, 2024Applicant: POWER INTEGRATIONS, INC.Inventors: ALEXEY KUDYMOV, LINLIN LIU, XIAOHUI WANG, JAMAL RAMDANI
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Publication number: 20240014308Abstract: A die seal ring including a two-dimensional electron gas is presented herein. A semiconductor device comprises an active device region. The active device region comprises a device terminal; and a die seal ring comprising a two dimensional electron gas region surrounds the active device region. By electrically coupling the device terminal to the two dimensional electron gas region, voltages at the semiconductor sidewall may be controlled to substantially equal that of the device terminal.Type: ApplicationFiled: August 27, 2021Publication date: January 11, 2024Applicant: Power Integrations, Inc.Inventors: Kuo-Chang Robert YANG, Alexey KUDYMOV, Kamal Raj VARADARAJAN, Alexei ANKOUDINOV, Sorin S. GEORGESCU
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Patent number: 11776815Abstract: A method of forming one or more contact regions in a high-voltage field effect transistor (HFET) includes providing a semiconductor material, including a first active layer and a second active layer, with a gate dielectric disposed on a surface of the semiconductor material. A first contact to the semiconductor material is formed that extends through the second active layer into the first active layer, and a passivation layer is deposited, where the gate dielectric is disposed between the passivation layer and the second active layer. An interconnect is formed extending through the first passivation layer and coupled to the first contact. An interlayer dielectric is deposited proximate to the interconnect, and a plug is formed extending into the interlayer dielectric and coupled to the first portion of the interconnect.Type: GrantFiled: May 25, 2022Date of Patent: October 3, 2023Assignee: Power Integrations, Inc.Inventors: Alexey Kudymov, LinLin Liu, Jamal Ramdani
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Patent number: 11721753Abstract: An HFET includes a first and second semiconductor material. A first composite passivation layer includes a first insulation layer and a first passivation layer, and the first passivation layer is disposed between the first insulation layer and the second semiconductor material. The HFET includes a second passivation layer, where the first insulation layer is disposed between the first passivation layer and the second passivation layer. A gate dielectric is disposed between the second semiconductor material and the first passivation layer. A source electrode and a drain electrode are coupled to the second semiconductor material, and a gate electrode is disposed laterally between the source electrode and the drain electrode. A first gate field plate is disposed between the first passivation layer and the second passivation layer and electrically connected to the gate electrode, and a second gate field plate is disposed above first gate field plate.Type: GrantFiled: June 29, 2021Date of Patent: August 8, 2023Assignee: POWER INTEGRATIONS, INC.Inventors: Alexey Kudymov, Linlin Liu, Xiaohui Wang, Jamal Ramdani
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Publication number: 20220406607Abstract: A method of forming one or more contact regions in a high-voltage field effect transistor (HFET) includes providing a semiconductor material, including a first active layer and a second active layer, with a gate dielectric disposed on a surface of the semiconductor material. A first contact to the semiconductor material is formed that extends through the second active layer into the first active layer, and a passivation layer is deposited, where the gate dielectric is disposed between the passivation layer and the second active layer. An interconnect is formed extending through the first passivation layer and coupled to the first contact. An interlayer dielectric is deposited proximate to the interconnect, and a plug is formed extending into the interlayer dielectric and coupled to the first portion of the interconnect.Type: ApplicationFiled: May 25, 2022Publication date: December 22, 2022Inventors: Alexey Kudymov, LinLin Liu, Jamal Ramdani
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Publication number: 20220264987Abstract: The present invention introduces an alarm circuit that detects potentially dangerous objects in the proximity during human activities, such as walking or running. The circuit is designed mostly to prevent stumbling for the people with temporary or permanent visual impairment conditions but can be used to prevent physical accidents under other circumstances as well. The circuit of the present invention can be permanently or temporarily mounted on human shoes, clothes, or other wearing means, including body parts. The placement of the circuit of the present invention includes but is not limited to the previously mentioned ones.Type: ApplicationFiled: February 20, 2021Publication date: August 25, 2022Applicant: Waddle Electronics LLCInventor: Alexey Kudymov
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Publication number: 20220262941Abstract: Capacitance networks for enhancing high voltage operation of high electron mobility transistors (HEMTs) are presented herein. A capacitance network, integrated and/or external, may be provided with a fixed number of capacitively coupled field plates to distribute the electric field in the drift region. The capacitively coupled field plates may advantageously be fabricated on the same metal layer to lower cost; and the capacitance network may be provided to control field plate potentials. The potentials on each field plate may be pre-determined through the capacitance network, resulting in a uniform, and/or a substantially uniform electric field distribution along the drift region.Type: ApplicationFiled: June 24, 2020Publication date: August 18, 2022Applicant: POWER INTEGRATIONS, INC.Inventors: KUO-CHANG YANG, SORIN GEORGESCU, ALEXEY KUDYMOV, KAMAL VARADARAJAN
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Patent number: 11373873Abstract: A method of forming one or more contact regions in a high-voltage field effect transistor (HFET) includes providing a semiconductor material, including a first active layer and a second active layer, with a gate dielectric disposed on a surface of the semiconductor material. A first contact to the semiconductor material is formed that extends through the second active layer into the first active layer, and a passivation layer is deposited, where the gate dielectric is disposed between the passivation layer and the second active layer. An interconnect is formed extending through the first passivation layer and coupled to the first contact. An interlayer dielectric is deposited proximate to the interconnect, and a plug is formed extending into the interlayer dielectric and coupled to the first portion of the interconnect.Type: GrantFiled: April 23, 2020Date of Patent: June 28, 2022Assignee: Power Integrations, Inc.Inventors: Alexey Kudymov, LinLin Liu, Jamal Ramdani
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Publication number: 20220013660Abstract: An HFET includes a first and second semiconductor material. A first composite passivation layer includes a first insulation layer and a first passivation layer, and the first passivation layer is disposed between the first insulation layer and the second semiconductor material. The HFET includes a second passivation layer, where the first insulation layer is disposed between the first passivation layer and the second passivation layer. A gate dielectric is disposed between the second semiconductor material and the first passivation layer. A source electrode and a drain electrode are coupled to the second semiconductor material, and a gate electrode is disposed laterally between the source electrode and the drain electrode. A first gate field plate is disposed between the first passivation layer and the second passivation layer and electrically connected to the gate electrode, and a second gate field plate is disposed above first gate field plate.Type: ApplicationFiled: June 29, 2021Publication date: January 13, 2022Applicant: Power Integrations, Inc.Inventors: Alexey Kudymov, Linlin Liu, Xiaohui Wang, Jamal Ramdani
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Patent number: 11075196Abstract: A heterostructure semiconductor device includes first and second active areas, each electrically isolated from one another, and each including first and second active layers with an electrical charge disposed therebetween. A power transistor is formed in the first active area, and an integrated gate resistor is formed in the second active area. A gate array laterally extends over the first active area of the power transistor. First and second ohmic contacts are respectively disposed at first and second lateral ends of the integrated gate resistor, the first and second ohmic contacts are electrically connected to the second portion of the second active layer, the second ohmic contact also being electrically connected to the gate array. A gate bus is electrically connected to the first ohmic contact.Type: GrantFiled: October 10, 2019Date of Patent: July 27, 2021Assignee: POWER INTEGRATIONS, INC.Inventors: Alexey Kudymov, Jamal Ramdani
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Patent number: 11075294Abstract: An HFET includes a first and second semiconductor material. A first composite passivation layer includes a first insulation layer and a first passivation layer, and the first passivation layer is disposed between the first insulation layer and the second semiconductor material. The HFET includes a second passivation layer, where the first insulation layer is disposed between the first passivation layer and the second passivation layer. A gate dielectric is disposed between the second semiconductor material and the first passivation layer. A source electrode and a drain electrode are coupled to the second semiconductor material, and a gate electrode is disposed laterally between the source electrode and the drain electrode. A first gate field plate is disposed between the first passivation layer and the second passivation layer and electrically connected to the gate electrode, and a second gate field plate is disposed above first gate field plate.Type: GrantFiled: March 19, 2020Date of Patent: July 27, 2021Assignee: POWER INTEGRATIONS, INC.Inventors: Alexey Kudymov, Linlin Liu, Xiaohui Wang, Jamal Ramdani
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Publication number: 20200287037Abstract: An HFET includes a first and second semiconductor material. A first composite passivation layer includes a first insulation layer and a first passivation layer, and the first passivation layer is disposed between the first insulation layer and the second semiconductor material. The HFET includes a second passivation layer, where the first insulation layer is disposed between the first passivation layer and the second passivation layer. A gate dielectric is disposed between the second semiconductor material and the first passivation layer. A source electrode and a drain electrode are coupled to the second semiconductor material, and a gate electrode is disposed laterally between the source electrode and the drain electrode. A first gate field plate is disposed between the first passivation layer and the second passivation layer and electrically connected to the gate electrode, and a second gate field plate is disposed above first gate field plate.Type: ApplicationFiled: March 19, 2020Publication date: September 10, 2020Applicant: Power Integrations, Inc.Inventors: Alexey KUDYMOV, Linlin LIU, Xiaohui WANG, Jamal RAMDANI
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Publication number: 20200258749Abstract: A method of forming one or more contact regions in a high-voltage field effect transistor (HFET) includes providing a semiconductor material, including a first active layer and a second active layer, with a gate dielectric disposed on a surface of the semiconductor material. A first contact to the semiconductor material is formed that extends through the second active layer into the first active layer, and a passivation layer is deposited, where the gate dielectric is disposed between the passivation layer and the second active layer. An interconnect is formed extending through the first passivation layer and coupled to the first contact. An interlayer dielectric is deposited proximate to the interconnect, and a plug is formed extending into the interlayer dielectric and coupled to the first portion of the interconnect.Type: ApplicationFiled: April 23, 2020Publication date: August 13, 2020Inventors: Alexey Kudymov, LinLin Liu, Jamal Ramdani
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Patent number: 10665463Abstract: A method of forming one or more contact regions in a high-voltage field effect transistor (HFET) includes providing a semiconductor material, including a first active layer and a second active layer, with a gate dielectric disposed on a surface of the semiconductor material. A first contact to the semiconductor material is formed that extends through the second active layer into the first active layer, and a passivation layer is deposited, where the gate dielectric is disposed between the passivation layer and the second active layer. An interconnect is formed extending through the first passivation layer and coupled to the first contact. An interlayer dielectric is deposited proximate to the interconnect, and a plug is formed extending into the interlayer dielectric and coupled to the first portion of the interconnect.Type: GrantFiled: December 14, 2018Date of Patent: May 26, 2020Assignee: Power Integrations, Inc.Inventors: Alexey Kudymov, LinLin Liu, Jamal Ramdani
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Patent number: 10629719Abstract: An HFET includes a first and second semiconductor material. A first composite passivation layer includes a first insulation layer and a first passivation layer, and the first passivation layer is disposed between the first insulation layer and the second semiconductor material. The HFET includes a second passivation layer, where the first insulation layer is disposed between the first passivation layer and the second passivation layer. A gate dielectric is disposed between the second semiconductor material and the first passivation layer. A source electrode and a drain electrode are coupled to the second semiconductor material, and a gate electrode is disposed laterally between the source electrode and the drain electrode. A first gate field plate is disposed between the first passivation layer and the second passivation layer and electrically connected to the gate electrode, and a second gate field plate is disposed above first gate field plate.Type: GrantFiled: September 27, 2018Date of Patent: April 21, 2020Assignee: Power Integrations, Inc.Inventors: Alexey Kudymov, Linlin Liu, Xiaohui Wang, Jamal Ramdani
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Publication number: 20200058640Abstract: A heterostructure semiconductor device includes first and second active areas, each electrically isolated from one another, and each including first and second active layers with an electrical charge disposed therebetween. A power transistor is formed in the first active area, and an integrated gate resistor is formed in the second active area. A gate array laterally extends over the first active area of the power transistor. First and second ohmic contacts are respectively disposed at first and second lateral ends of the integrated gate resistor, the first and second ohmic contacts are electrically connected to the second portion of the second active layer, the second ohmic contact also being electrically connected to the gate array. A gate bus is electrically connected to the first ohmic contact.Type: ApplicationFiled: October 10, 2019Publication date: February 20, 2020Inventors: Alexey Kudymov, Jamal Ramdani
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Patent number: 10490548Abstract: A heterostructure semiconductor device includes first and second active areas, each electrically isolated from one another, and each including first and second active layers with an electrical charge disposed therebetween. A power transistor is formed in the first active area, and an integrated gate resistor is formed in the second active area. A gate array laterally extends over the first active area of the power transistor. First and second ohmic contacts are respectively disposed at first and second lateral ends of the integrated gate resistor, the first and second ohmic contacts are electrically connected to the second portion of the second active layer, the second ohmic contact also being electrically connected to the gate array. A gate bus is electrically connected to the first ohmic contact.Type: GrantFiled: April 8, 2016Date of Patent: November 26, 2019Assignee: Power Integrations, Inc.Inventors: Alexey Kudymov, Jamal Ramdani
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Publication number: 20190139776Abstract: A method of forming one or more contact regions in a high-voltage field effect transistor (HFET) includes providing a semiconductor material, including a first active layer and a second active layer, with a gate dielectric disposed on a surface of the semiconductor material. A first contact to the semiconductor material is formed that extends through the second active layer into the first active layer, and a passivation layer is deposited, where the gate dielectric is disposed between the passivation layer and the second active layer. An interconnect is formed extending through the first passivation layer and coupled to the first contact. An interlayer dielectric is deposited proximate to the interconnect, and a plug is formed extending into the interlayer dielectric and coupled to the first portion of the interconnect.Type: ApplicationFiled: December 14, 2018Publication date: May 9, 2019Inventors: Alexey Kudymov, LinLin Liu, Jamal Ramdani
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Publication number: 20190096877Abstract: A heterostructure semiconductor device includes first and second active areas, each electrically isolated from one another, and each including first and second active layers with an electrical charge disposed therebetween. A power transistor is formed in the first active area, and an integrated gate resistor is formed in the second active area. A gate array laterally extends over the first active area of the power transistor. First and second ohmic contacts are respectively disposed at first and second lateral ends of the integrated gate resistor, the first and second ohmic contacts are electrically connected to the second portion of the second active layer, the second ohmic contact also being electrically connected to the gate array. A gate bus is electrically connected to the first ohmic contact.Type: ApplicationFiled: April 8, 2016Publication date: March 28, 2019Inventors: Alexey Kudymov, Jamal Ramdani
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Patent number: 10204791Abstract: A high-voltage field effect transistor (HFET) includes a first active layer, a second active layer, and a layer of electrical charge disposed proximate to the first active layer and the second active layer. A gate dielectric is disposed proximate to the second active layer. A contact region in the HFET includes a contact coupled to supply or withdraw charge from the HFET, and a passivation layer disposed proximate to the contact and the gate dielectric. An interconnect extends through the passivation layer and is coupled to the contact. An interlayer dielectric is disposed proximate to the interconnect, and a plug extends into the interlayer dielectric and is coupled to the first portion of the interconnect.Type: GrantFiled: September 22, 2017Date of Patent: February 12, 2019Assignee: Power Integrations, Inc.Inventors: Alexey Kudymov, LinLin Liu, Jamal Ramdani