Patents by Inventor Alexey L. Glebov

Alexey L. Glebov has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7127384
    Abstract: A fast transient simulator of SOI MOS circuits uses fast and accurate SOI transistor table models. The simulator uses a representation of a circuit with partitions. Each of partitions is simulated separately for a short time step by numerically solving differential equations describing its transient behavior. Behavior of the whole circuit is simulated in an event driven way where each event corresponds to an integration time step for each partition. Instead of body voltage, the simulator implements a transformation and uses body charge as an independent variable in order to obtain high accuracy and high speed of simulation. Construction of SOI transistor table models results in speed and accuracy enhancements. This transformation allows the reduction of the number of table dimensions exploiting the fact that SOI transistor backgate capacitance is approximately constant.
    Type: Grant
    Filed: August 27, 2002
    Date of Patent: October 24, 2006
    Assignee: Freescale semiconductor, Inc.
    Inventors: Vladimir P. Zolotov, Rajendran V. Panda, Sergey V. Gavrilov, Alexey L. Glebov, Yury B. Egorov, Dmitry Y. Nadexhin
  • Publication number: 20040044510
    Abstract: A fast transient simulator (71) of SOI MOS circuits uses fast and accurate SOI transistor table models (FIGS. 18, 19). The simulator uses a representation of a circuit with partitions (130). Each of partitions (130) is simulated separately for a short time step by numerically solving differential equations describing its transient behavior. Behavior of the whole circuit is simulated in an event driven way where each event corresponds to an integration time step for each partition. Instead of body voltage (Vy), the simulator (71) implements a transformation and uses body charge (Uy) as an independent variable in order to obtain high accuracy and high speed of simulation. Construction of SOI transistor table models (FIGS. 18, 19) results in speed and accuracy enhancements. This transformation allows the reduction of the number of table dimensions exploiting the fact that SOI transistor backgate capacitance is approximately constant.
    Type: Application
    Filed: January 17, 2003
    Publication date: March 4, 2004
    Inventors: Vladamir P Zolotov, Rajendran V Panda, Sergey V Gavrilov, Alexey L Glebov, Yury B Egorov, Dmitry Y Nadexhin