Patents by Inventor Alexey Sivtsov

Alexey Sivtsov has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and apparatus for reducing area and complexity of instruction wakeup logic in a multi-strand out-of-order processor
    Patent number: 9645819
    Abstract: A computer system, a computer processor and a method executable on a computer processor involve placing each sequence of a plurality of sequences of computer instructions being scheduled for execution in the processor into a separate queue. The head instruction from each queue is stored into a first storage unit prior to determining whether the head instruction is ready for scheduling. For each instruction in the first storage unit that is determined to be ready, the instruction is moved from the first storage unit to a second storage unit. During a first processor cycle, each instruction in the first storage unit that is determined to be not ready is retained in the first storage unit, and the determining of whether the instruction is ready is repeated during the next processor cycle. Scheduling logic performs scheduling of instructions contained in the second storage unit.
    Type: Grant
    Filed: June 15, 2012
    Date of Patent: May 9, 2017
    Assignee: Intel Corporation
    Inventors: Jayesh Iyer, Nikolay Kosarev, Sergey Shishlov, Alexey Sivtsov, Alexander Butuzov, Boris A. Babayan, Vladimir Penkovski
  • PROCESSOR LOGIC AND METHOD FOR DISPATCHING INSTRUCTIONS FROM MULTIPLE STRANDS
    Publication number: 20160364237
    Abstract: A processor includes logic to fetch an instruction stream divided into a plurality of strands for loading on one or more execution ports, identify a plurality of pending instructions, determine which of the strands are active, determine a program order of each of the pending instructions, and match the pending instructions to the execution ports based upon the program order of each pending instruction and whether each strand is active. Each pending instruction is at a respective head of one of the strands.
    Type: Application
    Filed: March 27, 2014
    Publication date: December 15, 2016
    Inventors: Nikolay Kosarev, Sergey Y. Shishlov, Alexey Sivtsov, Boris A. Babayan, Alexander V. Butuzov
  • METHOD AND APPARATUS FOR REDUCING AREA AND COMPLEXITY OF INSTRUCTION WAKEUP LOGIC IN A MULTI-STRAND OUT-OF-ORDER PROCESSOR
    Publication number: 20130339679
    Abstract: A computer system, a computer processor and a method executable on a computer processor involve placing each sequence of a plurality of sequences of computer instructions being scheduled for execution in the processor into a separate queue. The head instruction from each queue is stored into a first storage unit prior to determining whether the head instruction is ready for scheduling. For each instruction in the first storage unit that is determined to be ready, the instruction is moved from the first storage unit to a second storage unit. During a first processor cycle, each instruction in the first storage unit that is determined to be not ready is retained in the first storage unit, and the determining of whether the instruction is ready is repeated during the next processor cycle. Scheduling logic performs scheduling of instructions contained in the second storage unit.
    Type: Application
    Filed: June 15, 2012
    Publication date: December 19, 2013
    Applicant: INTEL CORPORATION
    Inventors: Jayesh IYER, Nikolay Kosarev, Sergey Shishlov, Alexey Sivtsov, Alexander Butuzov, Boris A. Babayan, Vladimir Penkovski