Patents by Inventor Alexey V. VERT

Alexey V. VERT has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230251510
    Abstract: Embodiments provide for an optical modulator that includes a first silicon region, a polycrystalline silicon region; a gate oxide region joining the first silicon region to a first side of the polycrystalline region; and a second silicon region formed on a second side of the polycrystalline silicon region opposite to the first side, thereby defining an active region of an optical modulator between the first silicon region, the polycrystalline region, the gate oxide region, and the second silicon region. The polycrystalline silicon region may be between 0 and 60 nanometers thick, and may be formed or patterned to the desired thickness. The second silicon region may be epitaxially grown from the polycrystalline silicon region and patterned into a desired cross sectional shape separately from or in combination with the polycrystalline silicon region.
    Type: Application
    Filed: April 11, 2023
    Publication date: August 10, 2023
    Inventors: Alexey V. VERT, Mark A. WEBSTER
  • Patent number: 11650439
    Abstract: Embodiments provide for an optical modulator that includes a first silicon region, a polycrystalline silicon region; a gate oxide region joining the first silicon region to a first side of the polycrystalline region; and a second silicon region formed on a second side of the polycrystalline silicon region opposite to the first side, thereby defining an active region of an optical modulator between the first silicon region, the polycrystalline region, the gate oxide region, and the second silicon region. The polycrystalline silicon region may be between 0 and 60 nanometers thick, and may be formed or patterned to the desired thickness. The second silicon region may be epitaxially grown from the polycrystalline silicon region and patterned into a desired cross sectional shape separately from or in combination with the polycrystalline silicon region.
    Type: Grant
    Filed: January 12, 2021
    Date of Patent: May 16, 2023
    Assignee: Cisco Technology, Inc.
    Inventors: Alexey V. Vert, Mark A. Webster
  • Patent number: 11480730
    Abstract: A method includes defining a first waveguide in a first region of an optical device over a first dielectric layer over a silicon on insulator (SOI) substrate of the optical device and disposing a second dielectric layer on the first waveguide and the first dielectric layer of the optical device. The method also includes defining a second region on the second dielectric layer, the first dielectric layer, and the SOI substrate. The second region includes an integrated trench structure defined in the SOI substrate. The method further includes etching the second region to form an etched second region, disposing a third dielectric layer in the etched second region, and disposing a second waveguide on at least the third dielectric layer. The second waveguide is disposed to provide an optical coupling between the second waveguide and the first waveguide.
    Type: Grant
    Filed: June 16, 2021
    Date of Patent: October 25, 2022
    Assignee: Cisco Technology, Inc.
    Inventors: Alexey V. Vert, Vipulkumar K. Patel, Mark A. Webster
  • Publication number: 20210311255
    Abstract: A method includes defining a first waveguide in a first region of an optical device over a first dielectric layer over a silicon on insulator (SOI) substrate of the optical device and disposing a second dielectric layer on the first waveguide and the first dielectric layer of the optical device. The method also includes defining a second region on the second dielectric layer, the first dielectric layer, and the SOI substrate. The second region includes an integrated trench structure defined in the SOI substrate. The method further includes etching the second region to form an etched second region, disposing a third dielectric layer in the etched second region, and disposing a second waveguide on at least the third dielectric layer. The second waveguide is disposed to provide an optical coupling between the second waveguide and the first waveguide.
    Type: Application
    Filed: June 16, 2021
    Publication date: October 7, 2021
    Inventors: Alexey V. VERT, Vipulkumar K. PATEL, Mark A. WEBSTER
  • Patent number: 11067750
    Abstract: Embodiments disclosed herein generally relate to optical coupling between a highly-confined waveguide region and a low confined waveguide region in an optical device. The low confined waveguide region includes a trench in a substrate of the optical device in order to provide additional dielectric layer thickness for insulation between the substrate of the optical device and waveguides for light signals having a low optical mode. The low confined waveguide region is coupled to the highly-confined waveguide region via a waveguide overlap and in some embodiments via an intermediary coupling waveguide.
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: July 20, 2021
    Assignee: Cisco Technology, Inc.
    Inventors: Alexey V. Vert, Vipulkumar K. Patel, Mark A. Webster
  • Publication number: 20210132420
    Abstract: Embodiments provide for an optical modulator that includes a first silicon region, a polycrystalline silicon region; a gate oxide region joining the first silicon region to a first side of the polycrystalline region; and a second silicon region formed on a second side of the polycrystalline silicon region opposite to the first side, thereby defining an active region of an optical modulator between the first silicon region, the polycrystalline region, the gate oxide region, and the second silicon region. The polycrystalline silicon region may be between 0 and 60 nanometers thick, and may be formed or patterned to the desired thickness. The second silicon region may be epitaxially grown from the polycrystalline silicon region and patterned into a desired cross sectional shape separately from or in combination with the polycrystalline silicon region.
    Type: Application
    Filed: January 12, 2021
    Publication date: May 6, 2021
    Inventors: Alexey V. VERT, Mark A. WEBSTER
  • Patent number: 10921619
    Abstract: Embodiments provide for an optical modulator that includes a first silicon region, a polycrystalline silicon region; a gate oxide region joining the first silicon region to a first side of the polycrystalline region; and a second silicon region formed on a second side of the polycrystalline silicon region opposite to the first side, thereby defining an active region of an optical modulator between the first silicon region, the polycrystalline region, the gate oxide region, and the second silicon region. The polycrystalline silicon region may be between 0 and 60 nanometers thick, and may be formed or patterned to the desired thickness. The second silicon region may be epitaxially grown from the polycrystalline silicon region and patterned into a desired cross sectional shape separately from or in combination with the polycrystalline silicon region.
    Type: Grant
    Filed: March 12, 2019
    Date of Patent: February 16, 2021
    Assignee: Cisco Technology, Inc.
    Inventors: Alexey V. Vert, Mark A. Webster
  • Publication number: 20200292853
    Abstract: Embodiments provide for an optical modulator that includes a first silicon region, a polycrystalline silicon region; a gate oxide region joining the first silicon region to a first side of the polycrystalline region; and a second silicon region formed on a second side of the polycrystalline silicon region opposite to the first side, thereby defining an active region of an optical modulator between the first silicon region, the polycrystalline region, the gate oxide region, and the second silicon region. The polycrystalline silicon region may be between 0 and 60 nanometers thick, and may be formed or patterned to the desired thickness. The second silicon region may be epitaxially grown from the polycrystalline silicon region and patterned into a desired cross sectional shape separately from or in combination with the polycrystalline silicon region.
    Type: Application
    Filed: March 12, 2019
    Publication date: September 17, 2020
    Inventors: Alexey V. VERT, Mark A. WEBSTER
  • Publication number: 20200241202
    Abstract: Embodiments disclosed herein generally relate to optical coupling between a highly-confined waveguide region and a low confined waveguide region in an optical device. The low confined waveguide region includes a trench in a substrate of the optical device in order to provide additional dielectric layer thickness for insulation between the substrate of the optical device and waveguides for light signals having a low optical mode. The low confined waveguide region is coupled to the highly-confined waveguide region via a waveguide overlap and in some embodiments via an intermediary coupling waveguide.
    Type: Application
    Filed: January 28, 2019
    Publication date: July 30, 2020
    Inventors: Alexey V. VERT, Vipulkumar K. PATEL, Mark A. WEBSTER