Abstract: The disclosure relates to a switchable termination resistance circuit for a transceiver physical layer interface. Example embodiments include a switchable termination resistance circuit (301) for a transmission line transceiver (801), the switchable termination resistance circuit (301) comprising: first and second terminals (TXP, TXN) for connection to a transmission line (103); first and second NMOS termination resistance switches (Mnsw1, Mnsw2) having source connections connected together at a midpoint node (303) and gate connections connected to an input node (304); a first resistor (R1) connected between the first terminal (TXP) and a drain connection of the first NMOS termination resistance switch (Mnsw1); a second resistor (R2) connected between the second terminal (TXN) and a drain connection of the second NMOS termination resistance switch (Mnsw2); and a Zener diode (Dz1) having a cathode side connected to the input node (304) and an anode side connected to the midpoint node (303).

Abstract: The disclosure relates to a switchable termination resistance circuit for a transceiver physical layer interface.

Abstract: A battery management system comprises a first and second battery cell controllers and a transmission line providing a point-to-point signal transmission path between the first and second battery cell controllers. At least one of the first and second battery cell controllers includes a logic circuit constructed and arranged for encoding data for transmission as a serial data stream along the signal transmission path in compliance with a multi-level encoding technique. The logic circuit comprises an encoding/decoding circuit that generates a modulated signal of the serial data stream over at least three discrete signal levels at a predetermined and fixed data pulse frequency for transmission through the transmission line and encodes a plurality of data units of the serial data stream into a data packet. The data packet includes at least three symbols constructed and arranged with at least four consecutive transmissions per symbol. Each transmission of each symbol assumes one of the three discrete signal levels.

Abstract: A battery management system comprises a first battery cell controller; a second battery cell controller, the first battery cell controller and the second battery cell controller each monitoring a plurality of battery cells; and a galvanically isolated transmission line providing a point-to-point signal transmission path between the first battery cell controller and the second battery cell controller.

Abstract: An integrated circuit for use in a differential network bus node comprising: a transceiver having a first transceiver input-output terminal and a second transceiver input-output terminal; a physical layer high terminal connected to the first transceiver input-output-terminal; a physical layer low terminal connected to the second transceiver input-output terminal; and a physical layer interface circuit comprising: a first low frequency RC matching circuit and a first high frequency RC matching circuit each connected between the first transceiver input-output-terminal and a first reference terminal; and a second low frequency RC matching circuit and a second high frequency RC matching circuit each connected between the second transceiver input-output terminal and a second reference terminal.

Abstract: Embodiments provide redundant voltage measurements for battery management systems. A first stack of battery cells is monitored with a first battery cell controller (BCC), and a second stack of battery cells is monitored with a second BCC. At least one battery cell is a common battery cell shared by the first stack of battery cells and the second stack of battery cells. For one embodiment, a single common battery cell is used. A failure of the first BCC or the second BCC is then determined based upon monitoring of the common battery cell. If failure is detected with respect to the BCGs, an action is taken to protect the battery pack including the first stack of battery cells and the second stack of battery cells. In addition, diagnostic voltage levels can also be used to facilitate the determination of a failure for the first BCC or the second BCC.

Abstract: A battery management system comprises a first battery cell controller; a second battery cell controller, the first battery cell controller and the second battery cell controller each monitoring a plurality of battery cells; and a galvanically isolated transmission line providing a point-to-point signal transmission path between the first battery cell controller and the second battery cell controller.

Abstract: A battery management system comprises a first and second battery cell controllers and a transmission line providing a point-to-point signal transmission path between the first and second battery cell controllers. At least one of the first and second battery cell controllers includes a logic circuit constructed and arranged for encoding data for transmission as a serial data stream along the signal transmission path in compliance with a multi-level encoding technique. The logic circuit comprises an encoding/decoding circuit that generates a modulated signal of the serial data stream over at least three discrete signal levels at a predetermined and fixed data pulse frequency for transmission through the transmission line and encodes a plurality of data units of the serial data stream into a data packet. The data packet includes at least three symbols constructed and arranged with at least four consecutive transmissions per symbol. Each transmission of each symbol assumes one of the three discrete signal levels.

Abstract: An integrated circuit (202) for use in a differential network bus node (200) comprising: a transceiver (212) having a first transceiver input-output terminal (214) and a second transceiver input-output terminal (216); a physical layer high terminal (208) connected to the first transceiver input-output-terminal (214); a physical layer low terminal (210) connected to the second transceiver input-output terminal (216); and a physical layer interface circuit (234) comprising: a first low frequency RC matching circuit (236) and a first high frequency RC matching circuit (240) each connected between the first transceiver input-output-terminal (214) and a first reference terminal (238); and a second low frequency RC matching circuit (242) and a second high frequency RC matching circuit (246) each connected between the second transceiver input-output terminal (216) and a second reference terminal (244).

Abstract: A detector (110) detects an unwanted oscillation generated by a closed-loop system (112) due to disconnection, improper usage, or absence of a stability-controlling element (104) necessary for the closed-loop system to function properly. An integrated circuit (102) includes the closed-loop system, the detector, and a supervisory system (114) that disables the closed-loop system upon disconnection of the stability-controlling element from the closed-loop system.

Abstract: A semiconductor device comprises a power transistor and a sense transistor. The power transistor conducts a power transistor current. The sense transistor conducts a sense transistor current substantially proportional to of the power transistor current. The power transistor and the sense transistor have drain source and a gate terminals, of which those of the sense transistor are arranged to be biased to those of the power transistor, respectively. The power transistor and the sense transistor each comprise: an inner region of type P?; an N-type buried layer; an N-type isolating barrier surrounding the inner region partially; an N-type source region in the inner region; an N-type drain region in the inner region. A barrier-to-drain connector connects the isolating barrier to the drain region, the one of the sense transistor has an electrical resistance which is higher than the resistance of the barrier-to-drain connector of the power transistor.

Abstract: A semiconductor device comprises a power transistor and a sense transistor. The power transistor conducts a power transistor current. The sense transistor conducts a sense transistor current substantially proportional to of the power transistor current. The power transistor and the sense transistor have drain source and a gate terminals, of which those of the sense transistor are arranged to be biased to those of the power transistor, respectively. The power transistor and the sense transistor each comprise: an inner region of type P?; an N-type buried layer; an N-type isolating barrier surrounding the inner region partially; an N-type source region in the inner region; an N-type drain region in the inner region. A barrier-to-drain connector connects the isolating barrier to the drain region, the one of the sense transistor has an electrical resistance which is higher than the resistance of the barrier-to-drain connector of the power transistor.