Abstract: A system may include a field programmable gate array (FPGA) based gateway comprising: a network interface configured to receive data packets containing proposed transactions, and validation logic circuitry configured to validate one or more headers or application-layer of the data packets in accordance with filter rules. The system may also include an FPGA based router comprising: a network interface configured to receive the data packets from the gateway, and parsing and lookup circuitry configured to compare the header field or application-layer field values in the data packets to those in a forwarding table. The system may also include an FPGA based matching engine comprising: a network interface configured to receive the data packets from the router, transaction validation circuitry configured to validate the proposed transactions based on information from state memory and policies, and matching algorithm circuitry configured to match pair of proposed transactions according to pre-determined criteria.

Abstract: The present disclosure relates to asymmetric read/write architectures for enhanced throughput and reduced latency. One example embodiment includes an integrated circuit. The integrated circuit includes a network interface. The integrated circuit also includes a communication bus interface. The integrated circuit is configured to establish a communication link with a processor of the host computing device over the communication bus interface, which includes mapping to memory addresses associated with the processor of the host computing device. The integrated circuit is also configured to receive payload data for transmission over the network interface in response to the processor of the host computing device writing payload data to the mapped memory addresses using one or more programmed input-outputs (PIOs). Further, the integrated circuit is configured to write payload data received over the network interface to the memory of the host computing device using direct memory access (DMA).

Abstract: A system may include a field programmable gate array (FPGA) based gateway comprising: a network interface configured to receive data packets containing proposed transactions, and validation logic circuitry configured to validate one or more headers or application-layer of the data packets in accordance with filter rules. The system may also include an FPGA based router comprising: a network interface configured to receive the data packets from the gateway, and parsing and lookup circuitry configured to compare the header field or application-layer field values in the data packets to those in a forwarding table. The system may also include an FPGA based matching engine comprising: a network interface configured to receive the data packets from the router, transaction validation circuitry configured to validate the proposed transactions based on information from state memory and policies, and matching algorithm circuitry configured to match pair of proposed transactions according to pre-determined criteria.

Abstract: An example embodiment may involve a network interface configured to transmit and receive frames. The embodiment may also involve a network protocol stack configured to: (i) perform encapsulation of outgoing messages into outgoing frames for transmission by way of the network interface, or (ii) perform decapsulation of incoming frames received by way of the network interface into incoming messages. The embodiment may also involve a parsing and validation module configured to: (i) receive representations of the incoming or the outgoing messages, and (ii) perform one or more validation checks on the representations, wherein the representations define transactions that are functionally equivalent to corresponding transactions that are defined by the messages, wherein the one or more validation checks are performed in parallel to performance of the encapsulation or decapsulation, and wherein a representation of a message failing the one or more validation checks causes the message to be discarded.

Abstract: The present disclosure relates to asymmetric read/write architectures for enhanced throughput and reduced latency. One example embodiment includes an integrated circuit. The integrated circuit includes a network interface. The integrated circuit also includes a communication bus interface. The integrated circuit is configured to establish a communication link with a processor of the host computing device over the communication bus interface, which includes mapping to memory addresses associated with the processor of the host computing device. The integrated circuit is also configured to receive payload data for transmission over the network interface in response to the processor of the host computing device writing payload data to the mapped memory addresses using one or more programmed input-outputs (PIOs). Further, the integrated circuit is configured to write payload data received over the network interface to the memory of the host computing device using direct memory access (DMA).

Abstract: An example embodiment may involve a network interface configured to transmit and receive frames. The embodiment may also involve a network protocol stack configured to: (i) perform encapsulation of outgoing messages into outgoing frames for transmission by way of the network interface, or (ii) perform decapsulation of incoming frames received by way of the network interface into incoming messages. The embodiment may also involve a parsing and validation module configured to: (i) receive representations of the incoming or the outgoing messages, and (ii) perform one or more validation checks on the representations, wherein the representations define transactions that are functionally equivalent to corresponding transactions that are defined by the messages, wherein the one or more validation checks are performed in parallel to performance of the encapsulation or decapsulation, and wherein a representation of a message failing the one or more validation checks causes the message to be discarded.

Abstract: An example embodiment may involve a network interface configured to transmit and receive frames. The embodiment may also involve a network protocol stack configured to: (i) perform encapsulation of outgoing messages into outgoing frames for transmission by way of the network interface, or (ii) perform decapsulation of incoming frames received by way of the network interface into incoming messages. The embodiment may also involve a parsing and validation module configured to: (i) receive representations of the incoming or the outgoing messages, and (ii) perform one or more validation checks on the representations, wherein the representations define transactions that are functionally equivalent to corresponding transactions that are defined by the messages, wherein the one or more validation checks are performed in parallel to performance of the encapsulation or decapsulation, and wherein a representation of a message failing the one or more validation checks causes the message to be discarded.

Abstract: The present disclosure relates to asymmetric read/write architectures for enhanced throughput and reduced latency. One example embodiment includes an integrated circuit. The integrated circuit includes a network interface. The integrated circuit also includes a communication bus interface. The integrated circuit is configured to establish a communication link with a processor of the host computing device over the communication bus interface, which includes mapping to memory addresses associated with the processor of the host computing device. The integrated circuit is also configured to receive payload data for transmission over the network interface in response to the processor of the host computing device writing payload data to the mapped memory addresses using one or more programmed input-outputs (PIOs). Further, the integrated circuit is configured to write payload data received over the network interface to the memory of the host computing device using direct memory access (DMA).

Abstract: An example embodiment may involve a network interface configured to transmit and receive frames. The embodiment may also involve a network protocol stack configured to: (i) perform encapsulation of outgoing messages into outgoing frames for transmission by way of the network interface, or (ii) perform decapsulation of incoming frames received by way of the network interface into incoming messages. The embodiment may also involve a parsing and validation module configured to: (i) receive representations of the incoming or the outgoing messages, and (ii) perform one or more validation checks on the representations, wherein the representations define transactions that are functionally equivalent to corresponding transactions that are defined by the messages, wherein the one or more validation checks are performed in parallel to performance of the encapsulation or decapsulation, and wherein a representation of a message failing the one or more validation checks causes the message to be discarded.

Abstract: An example embodiment may involve a network interface configured to transmit and receive frames. The embodiment may also involve a network protocol stack configured to: (i) perform encapsulation of outgoing messages into outgoing frames for transmission by way of the network interface, or (ii) perform decapsulation of incoming frames received by way of the network interface into incoming messages. The embodiment may also involve a parsing and validation module configured to: (i) receive representations of the incoming or the outgoing messages, and (ii) perform one or more validation checks on the representations, wherein the representations define transactions that are functionally equivalent to corresponding transactions that are defined by the messages, wherein the one or more validation checks are performed in parallel to performance of the encapsulation or decapsulation, and wherein a representation of a message failing the one or more validation checks causes the message to be discarded.