Abstract: A semiconductor wafer has a front side 1, a back side 2, a top layer 3, a bottom layer 4, an upper inner layer 5 lying below the top layer 3, a lower inner layer 6 lying above the bottom layer 4, a central region 7 between the layers 5 and 6 and an uneven distribution of crystal lattice defects. The concentration of the defects exhibits a first maximum (max1) in the central region 7 and a second maximum (max2) in the bottom layer 4.

Abstract: A semiconductor wafer has a front side 1, a back side 2, a top layer 3, a bottom layer 4, an upper inner layer 5 lying below the top layer 3, a lower inner layer 6 lying above the bottom layer 4, a central region 7 between the layers 5 and 6 an uneven distribution of crystal lattice defects. The concentration of the defects exhibits a first maximum (max1) in the central region 7 and a second maximum (max2) in the bottom layer 4.

Abstract: A semiconductor wafer has a front side 1, a back side 2, a top layer 3, a bottom layer 4, an upper inner layer 5 lying beneath the top layer 3, an lower inner layer 6 lying above the bottom layer 4, a central region 7 between the layers 5 and 6, and an uneven distribution of crystal lattice defects. The crystal lattice defects are substitutionally or interstitially included nitrogen or vacancies.

Abstract: A process for the heat treatment of semiconductor wafers, preferably monocrystalline ultrapure silicon wafers, using an upper and a lower heat source, which can be a plurality of upper and a plurality of lower lamps or banks of lamps. In the process chamber of an RTP system, the heat treatment is carried out on at least two wafers which are arranged parallel above one another, spaced apart, and are identical in terms of geometrical dimensions and thermal material properties.

Abstract: Point defects or impurities, which are detrimental to the quality of elecnic components, can be eliminated by means of rearsurface damage, which induces dislocations and/or stacking faults, by means of mechanical stress to the semiconductor wafers used in the manufacture of those components. For this purpose, the semiconductor wafers are brought into contact, before polishing, oxidation and thermal treatment, with moving carrier bodies covered with an elastic carrier medium having abrasive grain bonded to it, which creates the desired mechanical stress by forming a large number of very fine scratches and fissures in the surface of the semiconductor wafers.