Abstract: An emissive display device such as an active matrix electroluminescent display (AMEL display) has an improved method of operation. The AMEL display produces gray scale operation comprising an array of pixels, each pixel including a first transistor having its gate connected to a select line, its source connected to a data line, and its drain connected to the gate of a second transistor. The second transistor has its source adapted to receive a ramped voltage level, and its drain connected to a first electrode of an electroluminescent cell. The electroluminescent cell has a second electrode connected to an alternating current high voltage power source, wherein the electroluminescent cell is illuminated, when the ramp voltage level is less than a voltage level on the gate of the second transistor. The ramp voltage level is increased linearly during a frame duration, and the alternating current high voltage power source is on continuously during the same frame duration.

Abstract: In an active matrix electroluminescent display, a pixel containing a grounded conductive electric field shield between an EL cell and the switching electronics for the EL cell. In a method of fabricating the pixel, first, an EL cell switching circuit is formed, then an insulating layer is formed over the switching circuit and a conductive layer (the field shield) is formed over the insulating layer. A through hole is provided in the field shield such that an electrical connection can be made between the switching circuit and an EL cell. The EL cell is then conventionally formed on top of the shield layer. Consequently, the shield isolates the switching circuit from the EL cell and ensures that any electric fields produced in the EL cell do not interfere with the operation of the switching electronics. Furthermore, the switching circuitry for each cell contains two transistors; a low voltage MOS transistor and a high voltage MOS transistor.

Abstract: A Liquid Crystal Display device has first and second transparent substrates with a liquid crystal material sealed therebetween; a centrally disposed optically active display region having a matrix of pixels and a first and second scanner, and a transparent common electrode formed on the inner surface of the first and second transparent substrates, respectively; and a power supply and data signal distribution region surrounding at least a portion of the optically active display region and near the first and second scanners. The power supply and data signal distribution region comprises (a) a groove, and (b) a plurality of parallel conductors, formed on the inner surface of the second and first transparent substrates, respectively, which conductors include a height extending into the groove to reduce each conductor's resistance.

Abstract: A CMOS device is provided with a field shield region below one of the P and N channel MOS transistors, whereby the field shield region is formed to have the opposite conductivity of both the one MOS transistor it underlies, and of the substrate, thereby permitting the field shield region to be biased to a potential for turning off any anomalous back channel leakage current in the one MOS transistor, and also permitting the substrate to be biased to an opposite polarity for turning off such leakage current in the other MOS transistor.

Abstract: A three-mask process for fabricating liquid crystal devices enables the simultaneous fabrication of thin film transistors and conductor crossovers, thereby permitting the simultaneous fabrication of drive circuitry on the periphery of the devices.

Abstract: A memory cell has a first capacitance between a floating gate and a channel region and a second capacitance between a control gate and the floating gate. The second capacitance is less than said first capacitance, preferably much less, and there is self-alignment in two directions, resulting in a compact cell. The floating gate can have a textured surface facing the control gate. The control gate can also shift the cell operation from the enhancement mode into the depletion mode.

Abstract: A compact memory has a plurality of memory cells that are serially coupled. The plurality of cells are capacitively coupled to a substrate and directly coupled to switching circuits at both of its ends, which can disconnect the plurality of cells from a bit line at one end and a ground bus at the other end. An inhibit operation comprises precharging an array of pluralities of cells and the discharging of a selected plurality of cells. A WRITE operation comprises turning ON non-selected cells and then applying a programming voltage to a selected cell.

Abstract: A multilayer interconnect and method of forming the same between first and second overlying conductive strips separated by an insulating layer having an aperture therethrough. The improvement wherein at least one edge of the first strip is aligned with an overlying edge of the second strip. The interconnect is formed by depositing the second strip on the insulating layer such that it at least partially overlaps the aperture and extends beyond an edge of the first strip. The second strip and first strip are then partially removed such that at least one edge of the first and second conductive strips are aligned.

Abstract: A semiconductor device comprising an island of semiconductor material disposed on an insulating substrate is disclosed. A MOS transistor is formed in the semiconductor material, but the gate electrode does not extend over any sidewall of the silicon island. In order to electrically isolate the source and drain regions in the areas of the silicon island not subtended by the gate electrode, a pair of diodes in series is used to eliminate the shorting paths.

Abstract: A radiation hard memory cell comprises on an insulating substrate a low output impedance inverter made of a monocrystalline semiconductor and a high output impedance inverter made of a non-crystalline semiconductor in order to save space. The semiconductor can be Si and a barrier layer can be used. A method for making the cell comprises depositing and defining active layers, making gate insulating layers on the active layers, forming gates on the insulating layers, and forming source and drain regions in the active layers. One inverter can have its active and insulating layers formed before the remaining active layer is formed. The remaining active layer can then be simultaneously formed with the gate of the one active layer.

Abstract: A common island complementary-metal-oxide semiconductor device comprising an island of semiconductor material disposed on an insulating substrate is disclosed. Both N-channel and P-Channel transistors are formed in the common island of semiconductor material, but the gate electrode does not extend over the sidewalls of the silicon island. In order to electrically isolate the source and drain regions for each transistor, the areas of the silicon island outside of the channel region are doped with the appropriate dopants to form back-to-back diodes in series with respect to the source and drain regions. Additionally, a diode is disposed between both the N-channel and P-channel transistors to electrically isolate the two transistors.

Abstract: A multicolor filter for a display device includes separate filter elements for individually providing the primary colors of light. The areas of the filter elements are tailored in accordance with the percentages of primary light colors in pure white light, the percentages of primary light in the illuminating source, and the light transmission capabilities of the filter elements. Additionally, the filter elements are configured so that the centroid of the filter elements are within the close proximity of a straight line passing through adjacent filter elements.

Abstract: A process of forming a three region dielectric film on silicon and a semiconductor device employing such a film are disclosed. Silicon is oxidized in an oxygen-containing ambient. The oxidation step forms a first region of silicon oxide. Once oxidation has begun, reactive sputtering of aluminum in an oxygen plasma is initiated. This forms a second region of said dielectric film which comprises a mixture of silicon and aluminum oxides. A third region comprising substantially aluminum oxide is formed by the continuing reactive sputtering step.A semiconductor device comprising said three region dielectric film interposed between an electrode and a semiconductor body has little or no shift in threshold voltage providing good stability and can be fabricated in substantially less time and/or at lower temperatures than prior art methods.

Abstract: A semiconductor device comprising an island of semiconductor material disposed on an insulating substrate is disclosed. A MOS transistor is formed in the semiconductor island such that the gate electrode extends over the sidewalls of the island. Diodes are formed between the source and drain regions and the portions of the channel region along the sidewalls to electrically isolate the top transistor from the parasitic edge transistors.

Abstract: A method for forming a silicon dioxide layer on a silicon island on an insulating substrate includes the steps of initially providing an insulating substrate having a major surface on which a silicon island is disposed. The surface of the silicon island is then thermally oxidized and a silicon layer is deposited on the oxidized island and the portion of the substrate surface adjacent to the island. This entire silicon layer is then oxidized and a conductive polycrystalline silicon electrode is deposited thereon.

Abstract: A method for forming a layer of silicon dioxide over a silicon island on an insulating surface wherein the layer on top of the island is thinner than on the sidewalls is disclosed. The silicon island is oxidized and a silicon layer is deposited thereover. The layer of silicon is oxidized and the oxide layer is anisotropically etched until the top surface of the island is exposed, leaving oxide only on the sidewalls of the island. The exposed portion of the island is then oxidized to form a thin layer of gate oxide thereon. A conductive polycrystalline silicon electrode is deposited on the oxide-covered island. The disclosed method is particularly useful in the formation of MOSFETs.

Abstract: A method for forming a dielectric film over a semiconductor device is disclosed. The body of semiconductor material is formed and a hydrogen-containing silicon nitride material substantially free of silicon-hydrogen bonds is formed thereover.Also disclosed is a semiconductor device, including a body of semiconductor material and a dielectric film thereover. The dielectric film is a hydrogen-containing silicon nitride material substantially free of silicon-to-hydrogen bonds.

Abstract: A method for forming a layer of silicon dioxide over a silicon island on an insulating surface wherein the layer on top of the island is thinner than on the sidewalls is disclosed. The silicon island is oxidized and a silicon layer is deposited thereover. A layer of planarizing material is deposited over the silicon layer. The planarizing layer is anisotropically etched until the surface of the silicon layer overlying the island is exposed. The silicon layer is in turn etched until the surface of the oxide layer overlying the island is exposed. The remaining planarizing material is removed and the remaining silicon layer is oxidized. The thickness of the gate oxide layer on top of the island may be controlled by again exposing the island surface and reoxidizing to a predetermined thickness. A conductive polycrystalline silicon electrode is deposited on the oxide-covered island. The disclosed method is particularly useful in the formation of MOSFETs.

Abstract: A floating gate structure wherein the floating gate is a second level polysilicon layer that is substantially shielded from the substrate by a segmented, discontinuous first level word line. Coupling of the floating gate to the substrate for "writing" is accomplished by extending the floating gate between word line segments while electrical continuity of the word line is maintained by buried contacts which make electrical contact to a continuous third level polysilicon layer.

Abstract: An electrically alterable, nonvolatile floating gate memory device is described wherein the word line and the floating gate are arranged in a parallel relationship with the word line positioned above the floating gate and coincident therewith. A program line is oriented perpendicularly to both the floating gate and the word line in order to minimize the floating gate-program line capacitance and maximize the floating gate-word line capacitance. The net result of using such an arrangement is to reduce the disturbance of the non-selected cells during the write cycle and also to achieve a significant higher packing density.