Abstract: An exceptionally effective SoC design is achieved by the user of wrappers that comprise a functionally reconfigurable module (FRM) that is capable of affecting the operational functionality of the wrapper and that, consequently, is capable of affecting the operational functionality of a designed SoC. One embodiment of a core+wrapper combination comprises distinct input and output cells within the wrapper, and a separate FRM. Another embodiment may embed the input and output cells within the FRM. The FRM may be implemented with, for example, a field programmable logic array (FPLA). An additional advance is realized by providing a number of spare leads in the signal paths network that interconnects the various SoC elements.

Abstract: An exceptionally effective SoC design is achieved by the user of wrappers that comprise a functionally reconfigurable module (FRM) that is capable of affecting the operational functionality of the wrapper and that, consequently, is capable of affecting the operational functionality of a designed SoC. One embodiment of a core+wrapper combination comprises distinct input and output cells within the wrapper, and a separate FRM. Another embodiment may embed the input and output cells within the FRM. The FRM may be implemented with, for example, a field programmable logic array (FPLA). An additional advance is realized by providing a number of spare leads in the signal paths network that interconnects the various SoC elements.

Abstract: Fractional cycle stealing units are introduced in the routing of a programmable device such as an FPGA or FPSC to increase system performance resulting from the particular clock routing. The disclosed fractional cycle stealing units enable given amounts of clock skew between individual distribution sinks, and/or between logic paths that are in series. Each of the delay elements ‘steals’ a portion of a clock cycle (and perhaps one or more full clock cycles) from subsequent circuits to provide a more reliable logical function, and to avoid the need for overall additional clock cycles. These fractional cycle stealing elements offer a signal skew adjustment at the sinks of the distribution with no additional routing congestion expense. The disclosed cycle stealing delay elements are programmable, and enable clock skew between individual distribution sinks.

Abstract: Fractional cycle stealing units are introduced in the routing of a programmable device such as an FPGA or FPSC to increase system performance resulting from the particular clock routing. The disclosed fractional cycle stealing units enable given amounts of clock skew between individual distribution sinks, and/or between logic paths that are in series. Each of the delay elements ‘steals’ a portion of a clock cycle (and perhaps one or more full clock cycles) from subsequent circuits to provide a more reliable logical function, and to avoid the need for overall additional clock cycles. These fractional cycle stealing elements offer a signal skew adjustment at the sinks of the distribution with no additional routing congestion expense. The disclosed cycle stealing delay elements are programmable, and enable clock skew between individual distribution sinks.

Abstract: The output frequency of a simple low-power-dissipation oscillator circuit designed to drive PPS CMOS circuits is controlled by a closed-loop system. In response to deviations of the output frequency from a prescribed value, the system generates correction signals that are applied to an array of capacitors. In that way, capacitance is electrically added to or subtracted from a series-resonant path of the oscillator circuit, thereby to automatically establish and maintain the output frequency of the circuit at or near its prescribed value.

Abstract: Effective control of impedance values in integrated circuit applications is achieved with an integrated circuit transistor whose size is digitally controlled. The digitally controlled size is achieved, for example, with a parallel interconnection of MOS transistors. In one application, the digitally controlled transistor serves as a controlled impedance connected to an output terminal of an integrated circuit. In that application, a number of transistors are enabled with control signals, and the collection of enabled transistors is responsive to the input signal that normally is applied to a conventional transistor. In another application, where the digitally controlled transistor serves as a controlled impedance at the input of a circuit, only the control signals that enable transistors and thereby determine the effective developed impedance are employed.

Abstract: A method and apparatus for recovering the phase of a signal which may change at periodic intervals is disclosed which comprises gated variable frequency oscillators. These results are obtained in an illustrative embodiment of the present invention in which an incoming signal is fed into a gated oscillator and the complement of the incoming signal is fed into a matching gated oscillator. Advantageously, the respective outputs of the two oscillators are fed into a Boolean NOR gate. When the gated oscillators are designed to oscillate at the frequency of the incoming signal, the output waveform will have a bounded phase relationship with respect to the incoming signal.

Abstract: Effective control of impedance values in integrated circuit applications is achieved with an integrated circuit transistor whose size is digitally controlled. The digitally controlled size is achieved, for example, with a parallel interconnection of MOS transistors. In one application, the digitally controlled transitor serves as a controlled impedance connected to an output terminal of an integrated circuit. In that application, a number of transistors are enabled with control signals, and the collection of enabled transistors is responsive to the input signal that normally is applied to a conventional transistor. In another application, where the digitally controlled transistor serves as a controlled impedance at the input of a circuit, only the control signals that enable transistors and thereby determine the effective developed impedance are employed.

Abstract: A method and system for improving the design of an integrated circuit by iteratively analyzing the circuit and improving it with each iteration, until a preselected constraint is met. The design improvement is realized by selecting a model for the delay through each active element of the circuit that is characterized by a convex-function of the logarithm of the active element's size. Using the convex function model, with each iteration a static timing analysis of the circuit identifies the output that most grievously violates the specified constraint. With that output selected, an analysis of the path's timing structure identifies the active element in that path whose change in size would yield the largest improvement in performance. The size of that active element is adjusted accordingly and the iteration is repeated. For further improvement, the interconnection pattern of subnetworks of the circuit is evaluated and rearranged to improve performance.

Abstract: In laying out integrated circuits on a substrate, the placement of the components relative to each other is important in minimizing conductor area and hence chip area. Large scale integration often uses polycells which are lined up in rows to realize the digital logic circuitry. A partitioning procedure is disclosed which iteratively separates the cells into maximally connected subcells, eventually to assign them to rows so as to minimize conductor area. A technique called terminal propagation takes into account at every iteration the location of connections outside of the partitioned area. Rectilinear Steiner trees are generated to aid in terminal propagation.