Abstract: The invention relates to a controllable, temperature-compensated voltage limiter with a p.sup.+ np.sup.+ (or n.sup.+ pn.sup.+) semiconductor structure in which the width and doping of the central zone is selected such that no avalanche or Zener effect appears when voltage is applied to the two outer layers (punch-through diode). In accordance with the invention, the voltage U.sub.B to be limited is applied between the blocking pn-juncture (B-C). In addition, an adjustable auxiliary voltage (U.sub.H) is applied between the other pn-junction (H-C). The punch-through can be set to a higher defined value via the auxiliary voltage U.sub.H, this value being independent of the temperature to a large extent.