Abstract: A semiconductor device testing system, with a platform for supporting a semiconductor substrate, a light emitting system directed toward the platform, a controller, coupled to the light emitting system and adapted to selectively alter an operational parameter of the light emitting system, and a tester configured to characterize an electrical parameter of an electrical device formed in or over the semiconductor substrate while the electrical device is illuminated by one or more wavelengths of light emitted by the light emitting system under direction of the controller.

Abstract: An umbrella and cooling apparatus combination includes a housing having a top wall, a bottom wall and a peripheral wall. The top wall has a plurality of air inlets extending therethrough. A fastener attached to the top wall is removably attachable to a bottom side of a canopy. An elongated handle has a top end attached to the bottom wall. A screen is mounted in the housing and divides the housing into an upper compartment and a lower compartment. At least one duct is fluidly coupled to the lower compartment and has a free end extending outwardly from the housing. A fan assembly is mounted in the housing and is configured for directing air outwardly of the ducts when the fan assembly is turned on. Ice is positionable in the upper compartment and air moved through the ice and outwardly of the ducts so that the ice cools the air.

Abstract: A system (500) for removing wafer edge residue from a target wafer (508) is disclosed. A wafer holding mechanism (502) holds and optionally rotates the target wafer (508). A solution dispenser (504) applies a residue remover solution (506) to an edge/beveled surface at an outer edge of the wafer (508) by directing the residue remover solution (506) to a target location on the wafer (508) causing the residue remover solution (506) to come in contact with the edge surface of the wafer (508). The residue remover solution (506) contains an etch component that etches semiconductor material from the edge surface of the wafer (508). As a result, underlying semiconductor material below strongly adhered residue is removed thereby dislodging the strongly adhered residue.

Abstract: A system (500) removes wafer edge residue from a target wafer (508). A wafer holding mechanism (502) holds and rotates the target wafer (508). A residue remover mechanism (504) mechanically interacts or abrades an edge surface of the target wafer (508) and removes strongly adhered residue from the edge surface of the target wafer (508). The residue remover mechanism (504) controls coverage of the mechanical interaction and magnitude of the mechanical interaction.

Abstract: The present invention provides a method of forming a interconnect barrier layer 100. The method comprises physical vapor deposition of barrier material 200 within an opening 140 located in a dielectric layer 135 of a substrate 110. The method also comprises a RF plasma etching the barrier material 200 deposited in the opening 140 simultaneously with conducting the physical vapor deposition of the barrier material 200.

Abstract: There is disclosed a data receiving device for coupling to an AC power line through a standard light bulb socket. A standard medium lamp base is supported by a frame and connected to a branch circuit of the AC power line. An electrical device having signal terminals and supported by the frame is driven by electrical circuitry having a first input and a first output. The first output is coupled to the signal terminals for driving the electrical device. A data receiver has a second input for receiving both AC power and a data signal from the AC power line. The second input is coupled to the lamp base and a second output is coupled to the first input of the electrical circuitry. In another aspect, a data interface comprising a standard medium lamp base coupled to a data terminal device having a data receiving and/or transmitting interface circuit therein is threadably engaged to a standard medium lamp receptacle connected to the AC power line branch circuit.

Abstract: A method is disclosed to form a seed layer for an integrated circuit. The method may include depositing a metal seed layer (106) over a barrier layer (104) such that the metal seed layer (106) has a greater thickness along a top surface portion (114) of at least one recessed feature (102) formed in the substrate that is substantially coplanar with the substrate than a sidewall surface portion (112) of the at least one recessed feature (102). A portion of the metal seed layer (106) is etched from the top surface portion (114) of the at least one recessed feature (102) to improve coverage of the metal seed layer (106) along the sidewall surface portion (112) of the at least one recessed feature (102) and to mitigate overhang of the metal seed layer.

Abstract: Disclosed is a method of fabricating an integrated circuit comprising patterning a dielectric layer to form a hole having a sidewall and a bottom. The hole can expose an underlying material of an electrically conducting material. The method also includes exposing the sidewall and the exposed underlying material to a plasma etch, depositing a barrier layer on the bottom and the sidewall of the hole after the plasma etch clean, forming a counter-sunk cone in the underlying material by etching through the barrier layer at the bottom of the hole into the conducting metal underneath, flash depositing a thin layer of the barrier material into the hole, and finally depositing a metal seed layer in the hole covering the sidewalls and the bottom of the hole including the cone at the bottom. The hole is finally filled by depositing a metal layer in the hole.

Abstract: A multilevel metal and via structure is described. The metal conductors include a base or seed layer, a bulk conductor layer, a capping layer, and a barrier layer, and the via structure include a seed layer, a diffusion barrier layer and a metal plug. The via seed layer is controlled to a thickness that discourages the reaction between the via seed layer and the bulk conductor layer. The reaction may result in the formation of harmful voids at the bottom of the vias and is caused by having the via seed metal coming in contact with the bulk conductor through openings in the barrier layer.