Patents by Inventor Alfred Haeusler
Alfred Haeusler has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10696600Abstract: A method for producing a component includes a) providing at least two preforms each made of a carbon composite material, b) joining the at least two preforms at least at one respective connecting surface to form a composite, in which a joining compound is introduced between the joining surfaces of the preforms and then cured and the joining compound contains silicon carbide and at least one polymer adhesive, and c) siliconizing the composite to form the component. A component, such as an optical component produced thereby, is also provided.Type: GrantFiled: April 26, 2017Date of Patent: June 30, 2020Assignee: SGL Carbon SEInventors: Peter Polster, Andreas Kienzle, Thomas Putz, Albin Von Ganski, Blasius Hell, Alfred Haeusler
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Publication number: 20170226020Abstract: A method for producing a component includes a) providing at least two preforms each made of a carbon composite material, b) joining the at least two preforms at least at one respective connecting surface to form a composite, in which a joining compound is introduced between the joining surfaces of the preforms and then cured and the joining compound contains silicon carbide and at least one polymer adhesive, and c) siliconizing the composite to form the component. A component, such as an optical component produced thereby, is also provided.Type: ApplicationFiled: April 26, 2017Publication date: August 10, 2017Inventors: PETER POLSTER, ANDREAS KIENZLE, THOMAS PUTZ, ALBIN VON GANSKI, BLASIUS HELL, ALFRED HAEUSLER
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Patent number: 8703568Abstract: The present invention is a method for forming super steep doping profiles in MOS transistor structures. The method comprises forming a carbon containing layer (110) beneath the gate dielectric (50) and source and drain regions (80) of a MOS transistor. The carbon containing layer (110) will prevent the diffusion of dopants into the region (40) directly beneath the gate dielectric layer (50).Type: GrantFiled: January 26, 2012Date of Patent: April 22, 2014Assignee: Texas Instruments IncorporatedInventors: Jeffrey A. Babcock, Angelo Pinto, Scott Balster, Alfred Haeusler, Gregory E. Howard
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Publication number: 20140044979Abstract: A method for producing a component includes a) providing at least two preforms each made of a carbon composite material, b) joining the at least two preforms at least at one respective connecting surface to form a composite, in which a joining compound is introduced between the joining surfaces of the preforms and then cured and the joining compound contains silicon carbide and at least one polymer adhesive, and c) siliconizing the composite to form the component. A component, such as an optical component produced thereby, is also provided.Type: ApplicationFiled: October 21, 2013Publication date: February 13, 2014Applicant: SGL CARBON SEInventors: PETER POLSTER, ANDREAS KIENZLE, THOMAS PUTZ, ALBIN VON GANSKI, BLASIUS HELL, ALFRED HAEUSLER
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Patent number: 8648432Abstract: A fully embedded micromechanical device and a system on chip is manufactured on an SOI-substrate. The micromechanical device comprises a moveable component having a laterally extending upper and lower surface and vertical side surfaces. The upper surface is adjacent to an upper gap which laterally extends over at least a part of the upper surface and results from the removal of a shallow trench insulation material. The lower surface is adjacent to a lower gap which laterally extends over at least a part of the lower surface and results from the removal of the buried silicon oxide layer. The side surfaces of the movable component are adjacent to side gaps which surround at least a part of the vertical side surfaces of the moveable component and result from the removal of a deep trench insulation material.Type: GrantFiled: November 28, 2011Date of Patent: February 11, 2014Assignee: Texas Instruments Deutschland GmbHInventor: Alfred Haeusler
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Processes for producing a polymer-bonded fiber agglomerate and a fiber-reinforced composite material
Patent number: 8603374Abstract: A polymer-bonded fiber agglomerate includes short fibers selected from carbon, ceramic materials, glasses, metals and organic polymers, and a polymeric bonding resin selected from synthetic resins and thermoplastics. The fiber agglomerates have an average length, measured in the fiber direction, of from 3 mm to 50 mm and an average thickness, measured perpendicularly to the fiber direction, of from 0.1 mm to 10 mm. At least 75% of all of the contained fibers have a length which is at least 90% and not more than 110% of the fiber agglomerate average length. A fiber-reinforced composite material having the fiber agglomerate and processes for the production thereof are also provided.Type: GrantFiled: September 7, 2011Date of Patent: December 10, 2013Assignee: SGL Carbon SEInventors: Peter Domagalski, Alfred Haeusler, Ingrid Kraetschmer, Andreas Kienzle, Dieter Wuestner -
Publication number: 20130280906Abstract: A semiconductor device includes a buried layer and a deep contact for providing a low resistive connection to the buried layer. The deep contact is formed by doped polycrystalline silicon. A method of manufacturing a semiconductor device and a deep contact for providing a low resistive connection to the buried layer, with the steps of forming a buried layer, providing an active region adjacent the buried layer and forming a deep contact for providing a low resistive connection to the buried layer by patterning a contact shape for the deep contact on an upper surface of the active region, removing part of the active region underneath the contact shape to create a deep contact cavity. Subsequently a polycrystalline silicon layer for filling the deep contact cavity is deposited and doped.Type: ApplicationFiled: May 23, 2013Publication date: October 24, 2013Inventor: Alfred Haeusler
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Patent number: 8470679Abstract: A semiconductor device includes a buried layer and a deep contact for providing a low resistive connection to the buried layer. The deep contact is formed by doped polycrystalline silicon. A method of manufacturing a semiconductor device and a deep contact for providing a low resistive connection to the buried layer, with the steps of forming a buried layer, providing an active region adjacent the buried layer and forming a deep contact for providing a low resistive connection to the buried layer by patterning a contact shape for the deep contact on an upper surface of the active region, removing part of the active region underneath the contact shape to create a deep contact cavity. Subsequently a polycrystalline silicon layer for filling the deep contact cavity is deposited and doped.Type: GrantFiled: June 7, 2010Date of Patent: June 25, 2013Assignee: Texas Instruments Deutschland GmbHInventor: Alfred Haeusler
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Publication number: 20130134531Abstract: A fully embedded micromechanical device and a system on chip is manufactured on an SOI-substrate. The micromechanical device comprises a moveable component having a laterally extending upper and lower surface and vertical side surfaces. The upper surface is adjacent to an upper gap which laterally extends over at least a part of the upper surface and results from the removal of a shallow trench insulation material. The lower surface is adjacent to a lower gap which laterally extends over at least a part of the lower surface and results from the removal of the buried silicon oxide layer. The side surfaces of the movable component are adjacent to side gaps which surround at least a part of the vertical side surfaces of the moveable component and result from the removal of a deep trench insulation material.Type: ApplicationFiled: November 28, 2011Publication date: May 30, 2013Applicant: TEXAS INSTRUMENTS INCORPORATEDInventor: Alfred HAEUSLER
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Publication number: 20120205775Abstract: The invention relates to a method for manufacturing a semiconductor device. Accordingly, the trench processing sequence is changed and stress absorbing layers are applied. A shallow trench structure is etched. A deep trench structure is etched. A liner oxide is applied in the deep and shallow trench structure. An amorphous polysilicon liner is deposited on top of the liner oxide. A nitride liner is applied on top of the amorphous polysilicon liner, and the deep and shallow trenches are filled with oxide.Type: ApplicationFiled: February 14, 2012Publication date: August 16, 2012Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Alfred HAEUSLER, Wolfgang SCHWARTZ
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Publication number: 20120164802Abstract: The present invention is a method for forming super steep doping profiles in MOS transistor structures. The method comprises forming a carbon containing layer (110) beneath the gate dielectric (50) and source and drain regions (80) of a MOS transistor. The carbon containing layer (110) will prevent the diffusion of dopants into the region (40) directly beneath the gate dielectric layer (50).Type: ApplicationFiled: January 26, 2012Publication date: June 28, 2012Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Jeffrey A. Babcock, Angelo Pinto, Scott Balster, Alfred Haeusler, Gregory E. Howard
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Patent number: 8129246Abstract: The present invention is a method for forming super steep doping profiles in MOS transistor structures. The method comprises forming a carbon containing layer (110) beneath the gate dielectric (50) and source and drain regions (80) of a MOS transistor. The carbon containing layer (110) will prevent the diffusion of dopants into the region (40) directly beneath the gate dielectric layer (50).Type: GrantFiled: January 13, 2011Date of Patent: March 6, 2012Assignee: Texas Instruments IncorporatedInventors: Jeffrey A. Babcock, Angelo Pinto, Scott Balster, Alfred Haeusler, Gregory E. Howard
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Patent number: 8093115Abstract: A method of manufacturing a semiconductor device, the method comprising: taking an SOI substrate comprising a bulk substrate, a buried insulating layer and an active layer, and implanting the bulk substrate from the side of and through the insulating layer and the active layer so as to generate an area having an increased doping concentration in the bulk substrate at the interface between the bulk substrate and the insulating layer.Type: GrantFiled: September 21, 2010Date of Patent: January 10, 2012Assignee: Texas Instruments Deutschland GmbHInventors: Wolfgang Schwartz, Alfred Haeusler, Vladimir Frank Drobny
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PROCESSES FOR PRODUCING A POLYMER-BONDED FIBER AGGLOMERATE AND A FIBER-REINFORCED COMPOSITE MATERIAL
Publication number: 20110316179Abstract: A polymer-bonded fiber agglomerate includes short fibers selected from carbon, ceramic materials, glasses, metals and organic polymers, and a polymeric bonding resin selected from synthetic resins and thermoplastics. The fiber agglomerates have an average length, measured in the fiber direction, of from 3 mm to 50 mm and an average thickness, measured perpendicularly to the fiber direction, of from 0.1 mm to 10 mm. At least 75% of all of the contained fibers have a length which is at least 90% and not more than 110% of the fiber agglomerate average length. A fiber-reinforced composite material having the fiber agglomerate and processes for the production thereof are also provided.Type: ApplicationFiled: September 7, 2011Publication date: December 29, 2011Applicant: SGL CARBON AGInventors: PETER DOMAGALSKI, ALFRED HÄEUSLER, INGRID KÄRETSCHMER, ANDREAS KIENZLE, DIETER WÜESTNER -
Publication number: 20110111553Abstract: The present invention is a method for forming super steep doping profiles in MOS transistor structures. The method comprises forming a carbon containing layer (110) beneath the gate dielectric (50) and source and drain regions (80) of a MOS transistor. The carbon containing layer (110) will prevent the diffusion of dopants into the region (40) directly beneath the gate dielectric layer (50).Type: ApplicationFiled: January 13, 2011Publication date: May 12, 2011Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Jeffrey A. Babcock, Angelo Pinto, Scott Balster, Alfred Haeusler, Gregory E. Howard
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Publication number: 20110070719Abstract: A method of manufacturing a semiconductor device, the method comprising: taking an SOI substrate comprising a bulk substrate, a buried insulating layer and an active layer, and implanting the bulk substrate from the side of and through the insulating layer and the active layer so as to generate an area having an increased doping concentration in the bulk substrate at the interface between the bulk substrate and the insulating layer.Type: ApplicationFiled: September 21, 2010Publication date: March 24, 2011Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Wolfgang SCHWARTZ, Alfred HAEUSLER, Vladimir Frank DROBNY
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Patent number: 7888225Abstract: A method of manufacturing an electronic device including a PNP bipolar transistor comprises forming a collector in a substrate, depositing a base layer and an emitter layer on the substrate, and growing a nitride interface layer on the base layer as a base current modulation means, such that the nitride interface layer is arranged between the base layer and the emitter layer.Type: GrantFiled: February 23, 2009Date of Patent: February 15, 2011Assignee: Texas Instruments Deutschland GmbHInventor: Alfred Haeusler
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Patent number: 7883977Abstract: The present invention is a method for forming super steep doping profiles in MOS transistor structures. The method comprises forming a carbon containing layer (110) beneath the gate dielectric (50) and source and drain regions (80) of a MOS transistor. The carbon containing layer (110) will prevent the diffusion of dopants into the region (40) directly beneath the gate dielectric layer (50).Type: GrantFiled: January 20, 2009Date of Patent: February 8, 2011Assignee: Texas Instruments IncorporatedInventors: Jeffrey A. Babcock, Angelo Pinto, Scott Balster, Alfred Haeusler, Gregory E. Howard
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Publication number: 20100283119Abstract: A semiconductor device includes a buried layer and a deep contact for providing a low resistive connection to the buried layer. The deep contact is formed by doped polycrystalline silicon. A method of manufacturing a semiconductor device and a deep contact for providing a low resistive connection to the buried layer, with the steps of forming a buried layer, providing an active region adjacent the buried layer and forming a deep contact for providing a low resistive connection to the buried layer by patterning a contact shape for the deep contact on an upper surface of the active region, removing part of the active region underneath the contact shape to create a deep contact cavity. Subsequently a polycrystalline silicon layer for filling the deep contact cavity is deposited and doped.Type: ApplicationFiled: June 7, 2010Publication date: November 11, 2010Applicant: TEXAS INSTRUMENTS INCORPORATEDInventor: Alfred HAEUSLER
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Publication number: 20100148308Abstract: A method of manufacturing a semiconductor device comprises growing or depositing an implantation oxide layer, implanting a dopant, activating the dopant, and removing the implantation oxide layer after the step of activating the dopant.Type: ApplicationFiled: December 15, 2009Publication date: June 17, 2010Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Alfred HAEUSLER, Wolfgang SCHWARTZ