Patents by Inventor Alfred Haeusler

Alfred Haeusler has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10696600
    Abstract: A method for producing a component includes a) providing at least two preforms each made of a carbon composite material, b) joining the at least two preforms at least at one respective connecting surface to form a composite, in which a joining compound is introduced between the joining surfaces of the preforms and then cured and the joining compound contains silicon carbide and at least one polymer adhesive, and c) siliconizing the composite to form the component. A component, such as an optical component produced thereby, is also provided.
    Type: Grant
    Filed: April 26, 2017
    Date of Patent: June 30, 2020
    Assignee: SGL Carbon SE
    Inventors: Peter Polster, Andreas Kienzle, Thomas Putz, Albin Von Ganski, Blasius Hell, Alfred Haeusler
  • Publication number: 20170226020
    Abstract: A method for producing a component includes a) providing at least two preforms each made of a carbon composite material, b) joining the at least two preforms at least at one respective connecting surface to form a composite, in which a joining compound is introduced between the joining surfaces of the preforms and then cured and the joining compound contains silicon carbide and at least one polymer adhesive, and c) siliconizing the composite to form the component. A component, such as an optical component produced thereby, is also provided.
    Type: Application
    Filed: April 26, 2017
    Publication date: August 10, 2017
    Inventors: PETER POLSTER, ANDREAS KIENZLE, THOMAS PUTZ, ALBIN VON GANSKI, BLASIUS HELL, ALFRED HAEUSLER
  • Patent number: 8703568
    Abstract: The present invention is a method for forming super steep doping profiles in MOS transistor structures. The method comprises forming a carbon containing layer (110) beneath the gate dielectric (50) and source and drain regions (80) of a MOS transistor. The carbon containing layer (110) will prevent the diffusion of dopants into the region (40) directly beneath the gate dielectric layer (50).
    Type: Grant
    Filed: January 26, 2012
    Date of Patent: April 22, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Jeffrey A. Babcock, Angelo Pinto, Scott Balster, Alfred Haeusler, Gregory E. Howard
  • Publication number: 20140044979
    Abstract: A method for producing a component includes a) providing at least two preforms each made of a carbon composite material, b) joining the at least two preforms at least at one respective connecting surface to form a composite, in which a joining compound is introduced between the joining surfaces of the preforms and then cured and the joining compound contains silicon carbide and at least one polymer adhesive, and c) siliconizing the composite to form the component. A component, such as an optical component produced thereby, is also provided.
    Type: Application
    Filed: October 21, 2013
    Publication date: February 13, 2014
    Applicant: SGL CARBON SE
    Inventors: PETER POLSTER, ANDREAS KIENZLE, THOMAS PUTZ, ALBIN VON GANSKI, BLASIUS HELL, ALFRED HAEUSLER
  • Patent number: 8648432
    Abstract: A fully embedded micromechanical device and a system on chip is manufactured on an SOI-substrate. The micromechanical device comprises a moveable component having a laterally extending upper and lower surface and vertical side surfaces. The upper surface is adjacent to an upper gap which laterally extends over at least a part of the upper surface and results from the removal of a shallow trench insulation material. The lower surface is adjacent to a lower gap which laterally extends over at least a part of the lower surface and results from the removal of the buried silicon oxide layer. The side surfaces of the movable component are adjacent to side gaps which surround at least a part of the vertical side surfaces of the moveable component and result from the removal of a deep trench insulation material.
    Type: Grant
    Filed: November 28, 2011
    Date of Patent: February 11, 2014
    Assignee: Texas Instruments Deutschland GmbH
    Inventor: Alfred Haeusler
  • Patent number: 8603374
    Abstract: A polymer-bonded fiber agglomerate includes short fibers selected from carbon, ceramic materials, glasses, metals and organic polymers, and a polymeric bonding resin selected from synthetic resins and thermoplastics. The fiber agglomerates have an average length, measured in the fiber direction, of from 3 mm to 50 mm and an average thickness, measured perpendicularly to the fiber direction, of from 0.1 mm to 10 mm. At least 75% of all of the contained fibers have a length which is at least 90% and not more than 110% of the fiber agglomerate average length. A fiber-reinforced composite material having the fiber agglomerate and processes for the production thereof are also provided.
    Type: Grant
    Filed: September 7, 2011
    Date of Patent: December 10, 2013
    Assignee: SGL Carbon SE
    Inventors: Peter Domagalski, Alfred Haeusler, Ingrid Kraetschmer, Andreas Kienzle, Dieter Wuestner
  • Publication number: 20130280906
    Abstract: A semiconductor device includes a buried layer and a deep contact for providing a low resistive connection to the buried layer. The deep contact is formed by doped polycrystalline silicon. A method of manufacturing a semiconductor device and a deep contact for providing a low resistive connection to the buried layer, with the steps of forming a buried layer, providing an active region adjacent the buried layer and forming a deep contact for providing a low resistive connection to the buried layer by patterning a contact shape for the deep contact on an upper surface of the active region, removing part of the active region underneath the contact shape to create a deep contact cavity. Subsequently a polycrystalline silicon layer for filling the deep contact cavity is deposited and doped.
    Type: Application
    Filed: May 23, 2013
    Publication date: October 24, 2013
    Inventor: Alfred Haeusler
  • Patent number: 8470679
    Abstract: A semiconductor device includes a buried layer and a deep contact for providing a low resistive connection to the buried layer. The deep contact is formed by doped polycrystalline silicon. A method of manufacturing a semiconductor device and a deep contact for providing a low resistive connection to the buried layer, with the steps of forming a buried layer, providing an active region adjacent the buried layer and forming a deep contact for providing a low resistive connection to the buried layer by patterning a contact shape for the deep contact on an upper surface of the active region, removing part of the active region underneath the contact shape to create a deep contact cavity. Subsequently a polycrystalline silicon layer for filling the deep contact cavity is deposited and doped.
    Type: Grant
    Filed: June 7, 2010
    Date of Patent: June 25, 2013
    Assignee: Texas Instruments Deutschland GmbH
    Inventor: Alfred Haeusler
  • Publication number: 20130134531
    Abstract: A fully embedded micromechanical device and a system on chip is manufactured on an SOI-substrate. The micromechanical device comprises a moveable component having a laterally extending upper and lower surface and vertical side surfaces. The upper surface is adjacent to an upper gap which laterally extends over at least a part of the upper surface and results from the removal of a shallow trench insulation material. The lower surface is adjacent to a lower gap which laterally extends over at least a part of the lower surface and results from the removal of the buried silicon oxide layer. The side surfaces of the movable component are adjacent to side gaps which surround at least a part of the vertical side surfaces of the moveable component and result from the removal of a deep trench insulation material.
    Type: Application
    Filed: November 28, 2011
    Publication date: May 30, 2013
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Alfred HAEUSLER
  • Publication number: 20120205775
    Abstract: The invention relates to a method for manufacturing a semiconductor device. Accordingly, the trench processing sequence is changed and stress absorbing layers are applied. A shallow trench structure is etched. A deep trench structure is etched. A liner oxide is applied in the deep and shallow trench structure. An amorphous polysilicon liner is deposited on top of the liner oxide. A nitride liner is applied on top of the amorphous polysilicon liner, and the deep and shallow trenches are filled with oxide.
    Type: Application
    Filed: February 14, 2012
    Publication date: August 16, 2012
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Alfred HAEUSLER, Wolfgang SCHWARTZ
  • Publication number: 20120164802
    Abstract: The present invention is a method for forming super steep doping profiles in MOS transistor structures. The method comprises forming a carbon containing layer (110) beneath the gate dielectric (50) and source and drain regions (80) of a MOS transistor. The carbon containing layer (110) will prevent the diffusion of dopants into the region (40) directly beneath the gate dielectric layer (50).
    Type: Application
    Filed: January 26, 2012
    Publication date: June 28, 2012
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jeffrey A. Babcock, Angelo Pinto, Scott Balster, Alfred Haeusler, Gregory E. Howard
  • Patent number: 8129246
    Abstract: The present invention is a method for forming super steep doping profiles in MOS transistor structures. The method comprises forming a carbon containing layer (110) beneath the gate dielectric (50) and source and drain regions (80) of a MOS transistor. The carbon containing layer (110) will prevent the diffusion of dopants into the region (40) directly beneath the gate dielectric layer (50).
    Type: Grant
    Filed: January 13, 2011
    Date of Patent: March 6, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Jeffrey A. Babcock, Angelo Pinto, Scott Balster, Alfred Haeusler, Gregory E. Howard
  • Patent number: 8093115
    Abstract: A method of manufacturing a semiconductor device, the method comprising: taking an SOI substrate comprising a bulk substrate, a buried insulating layer and an active layer, and implanting the bulk substrate from the side of and through the insulating layer and the active layer so as to generate an area having an increased doping concentration in the bulk substrate at the interface between the bulk substrate and the insulating layer.
    Type: Grant
    Filed: September 21, 2010
    Date of Patent: January 10, 2012
    Assignee: Texas Instruments Deutschland GmbH
    Inventors: Wolfgang Schwartz, Alfred Haeusler, Vladimir Frank Drobny
  • Publication number: 20110316179
    Abstract: A polymer-bonded fiber agglomerate includes short fibers selected from carbon, ceramic materials, glasses, metals and organic polymers, and a polymeric bonding resin selected from synthetic resins and thermoplastics. The fiber agglomerates have an average length, measured in the fiber direction, of from 3 mm to 50 mm and an average thickness, measured perpendicularly to the fiber direction, of from 0.1 mm to 10 mm. At least 75% of all of the contained fibers have a length which is at least 90% and not more than 110% of the fiber agglomerate average length. A fiber-reinforced composite material having the fiber agglomerate and processes for the production thereof are also provided.
    Type: Application
    Filed: September 7, 2011
    Publication date: December 29, 2011
    Applicant: SGL CARBON AG
    Inventors: PETER DOMAGALSKI, ALFRED HÄEUSLER, INGRID KÄRETSCHMER, ANDREAS KIENZLE, DIETER WÜESTNER
  • Publication number: 20110111553
    Abstract: The present invention is a method for forming super steep doping profiles in MOS transistor structures. The method comprises forming a carbon containing layer (110) beneath the gate dielectric (50) and source and drain regions (80) of a MOS transistor. The carbon containing layer (110) will prevent the diffusion of dopants into the region (40) directly beneath the gate dielectric layer (50).
    Type: Application
    Filed: January 13, 2011
    Publication date: May 12, 2011
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jeffrey A. Babcock, Angelo Pinto, Scott Balster, Alfred Haeusler, Gregory E. Howard
  • Publication number: 20110070719
    Abstract: A method of manufacturing a semiconductor device, the method comprising: taking an SOI substrate comprising a bulk substrate, a buried insulating layer and an active layer, and implanting the bulk substrate from the side of and through the insulating layer and the active layer so as to generate an area having an increased doping concentration in the bulk substrate at the interface between the bulk substrate and the insulating layer.
    Type: Application
    Filed: September 21, 2010
    Publication date: March 24, 2011
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Wolfgang SCHWARTZ, Alfred HAEUSLER, Vladimir Frank DROBNY
  • Patent number: 7888225
    Abstract: A method of manufacturing an electronic device including a PNP bipolar transistor comprises forming a collector in a substrate, depositing a base layer and an emitter layer on the substrate, and growing a nitride interface layer on the base layer as a base current modulation means, such that the nitride interface layer is arranged between the base layer and the emitter layer.
    Type: Grant
    Filed: February 23, 2009
    Date of Patent: February 15, 2011
    Assignee: Texas Instruments Deutschland GmbH
    Inventor: Alfred Haeusler
  • Patent number: 7883977
    Abstract: The present invention is a method for forming super steep doping profiles in MOS transistor structures. The method comprises forming a carbon containing layer (110) beneath the gate dielectric (50) and source and drain regions (80) of a MOS transistor. The carbon containing layer (110) will prevent the diffusion of dopants into the region (40) directly beneath the gate dielectric layer (50).
    Type: Grant
    Filed: January 20, 2009
    Date of Patent: February 8, 2011
    Assignee: Texas Instruments Incorporated
    Inventors: Jeffrey A. Babcock, Angelo Pinto, Scott Balster, Alfred Haeusler, Gregory E. Howard
  • Publication number: 20100283119
    Abstract: A semiconductor device includes a buried layer and a deep contact for providing a low resistive connection to the buried layer. The deep contact is formed by doped polycrystalline silicon. A method of manufacturing a semiconductor device and a deep contact for providing a low resistive connection to the buried layer, with the steps of forming a buried layer, providing an active region adjacent the buried layer and forming a deep contact for providing a low resistive connection to the buried layer by patterning a contact shape for the deep contact on an upper surface of the active region, removing part of the active region underneath the contact shape to create a deep contact cavity. Subsequently a polycrystalline silicon layer for filling the deep contact cavity is deposited and doped.
    Type: Application
    Filed: June 7, 2010
    Publication date: November 11, 2010
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Alfred HAEUSLER
  • Publication number: 20100148308
    Abstract: A method of manufacturing a semiconductor device comprises growing or depositing an implantation oxide layer, implanting a dopant, activating the dopant, and removing the implantation oxide layer after the step of activating the dopant.
    Type: Application
    Filed: December 15, 2009
    Publication date: June 17, 2010
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Alfred HAEUSLER, Wolfgang SCHWARTZ