Abstract: Clock skew is minimized in an ASIC by grid-partitioning the IC chip into a number of preferably equal sized regions. An on-chip clock or buffer unit provides a clock signal to be distributed to buffers and clocked loads also on the IC. Equal length metal interconnect traces are formed in a preferably "H"-shaped configuration such that the termini and the center of the traces overlie buffer regions that will receive the distributed clock signal. Metallization interconnect paths are dictated by placement of joiner cells. By making each metal interconnect trace equal in overall length and in layer sub-lengths (if multiple metallization layers are present), clock skew along the interconnect traces is minimized macroscopically. A series of prioritized net lists is generated, defining interconnect paths to each region. A buffer is centrally located within each region, and is surrounded by a ring containing clocked loads to be coupled to the clock signal.