Abstract: An electronic device comprising a package comprising an encapsulated electronic chip, at least one at least partially exposed electrically conductive carrier lead for mounting the package on and electrically connecting the electronic chip to a carrier, and at least one at least partially exposed electrically conductive connection lead, and an electronic member stacked with the package so as to be mounted on and electrically connected to the package by the at least one connection lead.

Abstract: An electronic device comprising a package comprising an encapsulated electronic chip, at least one at least partially exposed electrically conductive carrier lead for mounting the package on and electrically connecting the electronic chip to a carrier, and at least one at least partially exposed electrically conductive connection lead, and an electronic member stacked with the package so as to be mounted on and electrically connected to the package by the at least one connection lead.

Abstract: A semiconductor package includes a substrate and a semiconductor chip which includes an active surface with a plurality of chip contact areas. The chip is electrically connected to the substrate. The substrate includes a sheet of core material, a plurality of upper conducting traces and upper contact pads on its upper surface, a second plurality of lower conductive traces and external contact areas on its bottom surface. A plurality of conducting vias connect the conducting traces and lower conducting traces. The substrate also includes a plurality of vent holes and a layer of solder resist covering the upper and lower surfaces of the substrate leaving the contact areas free from solder resist.