Abstract: Method and apparatus to avoid the code space and time overhead of the software-loop. Loops (repeatedly executed blocks of instructions) are often used in software and microcode. Loops may be employed for array manipulation, storage initialization, division and square-root interpretation, and microinterpretation of instructions with variable-length operands. Software creates loops by keeping an iteration count in a register or in memory. During each iteration of the code loop, software decrements the count, and then branches to the "top" of the loop is the count remains nonzero. This apparatus puts the decrement, compare, and branch-to-top into hardware, reducing the number of instructions in the loop and speeding loop execution. Hardware further speeds loop execution by eliminating the wait for the branch to the top-of-loop instruction. That is, it prefetches the top-of-loop instruction near the bottom of the loop.

Abstract: An address translation mechanism that allows for the creation, use, and purging of Translation Lookaside Buffer (TLB) entries associated to a unique task (virtual machine or guest). This association between guest and TLB entry allows for reuse of guest TLB entries (sets) in a multitasking system, quick purging of TLB entries during transition between address translation states, and quick restoration of control program TLB entries.The address translation mechanism as described herein must contain, at a minimum, a translation lookaside buffer; each entry must contain, at least: a absolute address field, a virtual address field and a translation mode indicator (TMI); a guest TMI table having entries containing a unique identifier to a guest and an associated TMI value; and a TMI register that holds the currently valid TMI.

Abstract: A plurality of processors are connected to the interprocessor communications facility in the multiprocessing system of the invention. The interprocessor communications facility has arbitration circuitry, mailbox circuitry, and processor interrupt circuitry. The interprocessor communications facility of the invention is centralized and does not require the use of main storage. This enables processors to communicate with each other in a fast and efficient manner. The arbitration circuitry prevents simultaneous access of the interprocessor communications facility by more than one processor, and decodes the commands sent from the processors and routes them to the processor interrupt circuitry or to the mailbox circuitry, depending on the command. The mailbox circuitry of the invention receives messages from sending processors and provides them to the intended receiving processors in a safe and secure manner.