Patents by Inventor Alfred Vater

Alfred Vater has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180047582
    Abstract: A method of manufacturing a semiconductor device includes forming an etching mask over a semiconductor body, forming a plurality of trenches in the semiconductor body to define a plurality of protruding semiconductor portions between adjacent trenches, and forming a protection layer in contact with a semiconductor material of the protruding semiconductor portions. The method further includes performing a wet etching step to remove portions of the etching mask and, thereafter, treating the semiconductor body with a mixture of hydrofluoric acid and ethylene glycol and bringing the semiconductor material of sidewalls of the plurality of protruding semiconductor portions into contact with the mixture of hydrofluoric acid and ethylene glycol.
    Type: Application
    Filed: August 8, 2017
    Publication date: February 15, 2018
    Inventors: Marko Lemke, Alfred Vater, Carsten Moritz
  • Patent number: 9418864
    Abstract: In one embodiment, a method of forming a semiconductor device is disclosed. A high-k dielectric is deposited of over a semiconductor body, and a portion of the high-k dielectric is wet etched an etchant selected from the group consisting of hot phos, piranha, and SC1.
    Type: Grant
    Filed: January 30, 2008
    Date of Patent: August 16, 2016
    Assignee: Infineon Technologies AG
    Inventors: Danny Pak-Chum Shum, Alfred Vater, John Power, Wolfram Langheinrich, Ulrike Bewersdorff-Sarlette
  • Patent number: 9230885
    Abstract: One or more embodiments relate to a method for forming a semiconductor structure, comprising: providing a workpiece; forming a dielectric barrier layer over the workpiece; forming an opening through the dielectric barrier layer; forming a seed layer over the dielectric barrier layer and within the dielectric barrier layer opening; and electroplating a first fill layer on the seed layer.
    Type: Grant
    Filed: October 23, 2013
    Date of Patent: January 5, 2016
    Assignee: Infineon Technologies AG
    Inventors: Dirk Meinhold, Gerald Dallmann, Alfred Vater
  • Publication number: 20150147839
    Abstract: A method for manufacturing a semiconductor device may include: forming a metal layer structure over a semiconductor workpiece; forming a first layer over the metal layer structure, the first layer including a first material; forming at least one opening in the first layer and the metal layer structure; depositing a second layer to fill the at least one opening and at least partially cover a surface of the first layer facing away from the metal layer structure, the second layer including a second material that is different from the first material; removing the second layer from at least the surface of the first layer facing away from the metal layer structure; and removing the first layer.
    Type: Application
    Filed: November 26, 2013
    Publication date: May 28, 2015
    Applicant: Infineon Technologies Dresden GmbH
    Inventors: Alessia Scire, Alfred Vater, Mirko Vogt, Momtchil Stavrev, Tarja Hauck, Bee Kim Hong, Heiko Estel
  • Patent number: 9041162
    Abstract: A wafer includes a plurality of chips, each of the chips being spaced from each other by kerf-line regions including a reduced width.
    Type: Grant
    Filed: February 24, 2014
    Date of Patent: May 26, 2015
    Assignee: Infineon Technologies AG
    Inventors: Giuseppe Miccoli, Bhaskaran Jayachandran, Friedrich Steffen, Alfred Vater
  • Publication number: 20140319688
    Abstract: In one embodiment, a method of forming a semiconductor device includes forming a metal line over a substrate and depositing an alloying material layer over a top surface of the metal line. The method further includes forming a protective layer by combining the alloying material layer with the metal line.
    Type: Application
    Filed: July 8, 2014
    Publication date: October 30, 2014
    Inventors: Dirk Meinhold, Norbert Mais, Reimund Engl, Hans-Joerg Timme, Alfred Vater, Stephan Henneck, Norbert Urbansky
  • Patent number: 8835319
    Abstract: In one embodiment, a method of forming a semiconductor device includes forming a metal line over a substrate and depositing an alloying material layer over a top surface of the metal line. The method further includes forming a protective layer by combining the alloying material layer with the metal line.
    Type: Grant
    Filed: March 2, 2012
    Date of Patent: September 16, 2014
    Assignee: Infineon Technologies AG
    Inventors: Dirk Meinhold, Norbert Mais, Reimund Engl, Hans-Joerg Timme, Alfred Vater, Stephan Henneck, Norbert Urbansky
  • Publication number: 20140167226
    Abstract: A wafer includes a plurality of chips, each of the chips being spaced from each other by kerf-line regions including a reduced width.
    Type: Application
    Filed: February 24, 2014
    Publication date: June 19, 2014
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Giuseppe Miccoli, Bhaskaran Jayachandran, Friedrich Steffen, Alfred Vater
  • Patent number: 8680653
    Abstract: A wafer includes a plurality of chips, each of the chips being spaced from each other by kerf-line regions including a reduced width.
    Type: Grant
    Filed: November 12, 2007
    Date of Patent: March 25, 2014
    Assignee: Infineon Technologies AG
    Inventors: Giuseppe Miccoli, Bhaskaran Jayachandran, Friedrich Steffen, Alfred Vater
  • Publication number: 20140077379
    Abstract: One or more embodiments relate to a method for forming a semiconductor structure, comprising: providing a workpiece; forming a dielectric barrier layer over the workpiece; forming an opening through the dielectric barrier layer; forming a seed layer over the dielectric barrier layer and within the dielectric barrier layer opening; and electroplating a first fill layer on the seed layer.
    Type: Application
    Filed: October 23, 2013
    Publication date: March 20, 2014
    Inventors: Meinhold DIRK, Gerald DALLMANN, Alfred VATER
  • Patent number: 8580687
    Abstract: One or more embodiments relate to a method for forming a semiconductor structure, comprising: providing a workpiece; forming a dielectric barrier layer over the workpiece; forming an opening through the dielectric barrier layer; forming a seed layer over the dielectric barrier layer and within the dielectric barrier layer opening; and electroplating a first fill layer on the seed layer.
    Type: Grant
    Filed: September 30, 2010
    Date of Patent: November 12, 2013
    Assignee: Infineon Technologies AG
    Inventors: Gerald Dallmann, Dirk Meinhold, Alfred Vater
  • Publication number: 20130228929
    Abstract: In one embodiment, a method of forming a semiconductor device includes forming a metal line over a substrate and depositing an alloying material layer over a top surface of the metal line. The method further includes forming a protective layer by combining the alloying material layer with the metal line.
    Type: Application
    Filed: March 2, 2012
    Publication date: September 5, 2013
    Applicant: Infineon Technologies AG
    Inventors: Dirk Meinhold, Norbert Mais, Reimund Engl, Hans-Joerg Timme, Alfred Vater, Stephan Henneck, Norbert Urbansky
  • Publication number: 20120080795
    Abstract: One or more embodiments relate to a method for forming a semiconductor structure, comprising: providing a workpiece; forming a dielectric barrier layer over the workpiece; forming an opening through the dielectric barrier layer; forming a seed layer over the dielectric barrier layer and within the dielectric barrier layer opening; and electroplating a first fill layer on the seed layer.
    Type: Application
    Filed: September 30, 2010
    Publication date: April 5, 2012
    Inventors: Gerald DALLMANN, Dirk MEINHOLD, Alfred VATER
  • Publication number: 20090189280
    Abstract: In one embodiment, a method of forming a semiconductor device is disclosed. A high-k dielectric is deposited of over a semiconductor body, and a portion of the high-k dielectric is wet etched an etchant selected from the group consisting of hot phos, piranha, and SC1.
    Type: Application
    Filed: January 30, 2008
    Publication date: July 30, 2009
    Inventors: Daniel Pak-Chum Shum, Alfred Vater, John Power, Wolfram Langheinrich, Ulrike Bewersdorff-Sarlette
  • Publication number: 20090121321
    Abstract: A wafer includes a plurality of chips, each of the chips being spaced from each other by kerf-line regions including a reduced width.
    Type: Application
    Filed: November 12, 2007
    Publication date: May 14, 2009
    Inventors: Giuseppe Miccoli, Bhaskaran Jayachandran, Friedrich Steffen, Alfred Vater