Patents by Inventor Alfred Y. Cho

Alfred Y. Cho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4686550
    Abstract: Heterojunction devices having doping interface dipoles near the heterojunction interface are disclosed. The doping interface dipoles comprise two charge sheets of different conductivity type which are positioned within a carrier mean free path of the heterojunction interface.
    Type: Grant
    Filed: December 4, 1984
    Date of Patent: August 11, 1987
    Assignee: American Telephone and Telegraph Company, AT&T Bell Laboratories
    Inventors: Federico Capasso, Alfred Y. Cho
  • Patent number: 4679061
    Abstract: Photoconductive gain is observed in a device comprising a superlattice having well and barrier layers, and cladding layers on the opposite sides of the superlattice with the barrier layers of the superlattice having an energy bandgap greater than the bandgap of the cladding layers.
    Type: Grant
    Filed: June 14, 1985
    Date of Patent: July 7, 1987
    Assignee: American Telephone and Telegraph Company, AT&T Bell Laboratories
    Inventors: Federico Capasso, Alfred Y. Cho, Albert L. Hutchinson, Khalid Mohammed
  • Patent number: 4599728
    Abstract: A multi-quantum well laser having a Ga.sub.0.47 In.sub.0.53 As/Al.sub.0.48 In.sub.0.52 As active region emitting at 1.55 .mu.m and well layers having a thickness less than 150 Angstroms.
    Type: Grant
    Filed: July 11, 1983
    Date of Patent: July 8, 1986
    Assignee: AT&T Bell Laboratories
    Inventors: Kambiz Alavi, Alfred Y. Cho, Thomas P. Pearsall, Henryk Temkin
  • Patent number: 4553155
    Abstract: A high speed bias-free photodetector which capacitively couples the output signal to an external circuit is described.
    Type: Grant
    Filed: March 22, 1984
    Date of Patent: November 12, 1985
    Assignee: AT&T Bell Laboratories
    Inventors: Chung Y. Chen, Alfred Y. Cho
  • Patent number: 4534103
    Abstract: A metal gate field effect transistor has its source and drain located on one major surface of a gallium arsenide layer, while its gate electrode forms a Schottky barrier contact to an opposed major surface of the layer in a self-aligned relationship to the source and drain.
    Type: Grant
    Filed: June 25, 1982
    Date of Patent: August 13, 1985
    Assignee: AT&T Bell Laboratories
    Inventors: Alfred Y. Cho, Bernard Glance, Daniel Lubzens, Martin V. Schneider
  • Patent number: 4471367
    Abstract: A thin and highly doped Ga.sub.0.47 In.sub.0.53 As layer disposed on a Ga.sub.0.47 In.sub.0.53 As layer increases the barrier height and produces useful device characteristics. For example, the structure may be used as the gate electrode in an InGaAs field effect transistor.
    Type: Grant
    Filed: December 4, 1981
    Date of Patent: September 11, 1984
    Assignee: AT&T Bell Laboratories
    Inventors: Chung Y. Chen, Alfred Y. Cho
  • Patent number: 4471370
    Abstract: A majority carrier photodetector has high sensitivity and fast response times. The photodetector comprises a thin highly doped layer surrounded on either side by two nominally undoped layers which are completely depleted at thermal equilibrium.
    Type: Grant
    Filed: April 24, 1981
    Date of Patent: September 11, 1984
    Assignee: AT&T Bell Laboratories
    Inventors: Chung Y. Chen, Alfred Y. Cho
  • Patent number: 4297783
    Abstract: Surface recombination current in GaAs devices is reduced by means of a semi-insulating, oxygen, iron or chromium doped monocrystalline layer of AlGaAs grown by MBE. The AlGaAs layer is grown on a GaAs body and is then masked. Diffusion of suitable impurities through a window in the mask converts the exposed portions of the AlGaAs layer to low resistivity and modifies the conductivity of the underlying zone of the GaAs body. The peripheral portions of the AlGaAs layer, however, remain semi-insulating and are effective to reduce the surface recombination velocity - diffusion length product by more than an order of magnitude.
    Type: Grant
    Filed: April 21, 1980
    Date of Patent: November 3, 1981
    Assignee: Bell Telephone Laboratories, Incorporated
    Inventors: Horace C. Casey, Jr., Alfred Y. Cho, Philip W. Foy
  • Patent number: 4249190
    Abstract: A planar field effect transistor (FET) includes a plurality of spaced-apart, floating Schottky barrier, epitaxial metal gate electrodes which are embedded within a semiconductor body. A drain electrode and a gate control electrode are formed on one major surface of the body whereas a source electrode, typically grounded, is formed on an opposite major surface of the body. The FET channel extends vertically between the source and drain, and current flow therein is controlled by application of suitable gate voltage. Two modes of operation are possible: (1) the depletion regions of the control gates and the floating gates pinch off the channel so that with zero control gate voltage no current flows from source to drain; then, forward biasing the control gate opens the channel; and (2) the depletion regions of the control gates and the floating gates do not pinch off the channel, but reverse biasing the control gate produces pinch off.
    Type: Grant
    Filed: July 5, 1979
    Date of Patent: February 3, 1981
    Assignee: Bell Telephone Laboratories, Incorporated
    Inventor: Alfred Y. Cho
  • Patent number: 4239955
    Abstract: The effusion cell for molecular beam epitaxy apparatus consists of a pyrolytic BN cylindrical crucible surrounded by a heating coil. The position of the heating coil is maintained by a plurality of ceramic rods extending parallel to the cylinder axis with notches along their length for engaging the heating coil. The ceramic rods are secured by a retaining ring near the front of the crucible and an apertured disk near the back of the crucible. The entire assembly is surrounded by a foil heat shield.
    Type: Grant
    Filed: October 30, 1978
    Date of Patent: December 16, 1980
    Assignee: Bell Telephone Laboratories, Incorporated
    Inventor: Alfred Y. Cho
  • Patent number: 4236122
    Abstract: Parallel channels are separated by ridges formed in a semiconductor body in such a way that each channel is wider at its base than at its top. Molecular beam epitaxy is used to deposit semiconductor layers on the ridges and in the channels. Because each channel is narrower at its top than at its base, the configuration is essentially self-masking. That is, the layers in the channel are physically separate from those on the ridges, as would be metallic contacts deposited on the layers. This technique is employed in the fabrication of a plurality of self-aligned, stripe geometry, mesa double heterostructure junction lasers.
    Type: Grant
    Filed: April 26, 1978
    Date of Patent: November 25, 1980
    Assignee: Bell Telephone Laboratories, Incorporated
    Inventors: Alfred Y. Cho, Won-Tien Tsang
  • Patent number: 4236166
    Abstract: A vertical field effect transistor (10) includes a relatively wide bandgap, lowly doped active layer (18) epitaxially grown on, and substantially lattice matched to, an underlying semiconductor body portion (13). A mesa (20) of lower bandgap material is epitaxially grown on and substantially lattice matched to the active layer. A source electrode (22) is formed on a bottom major surface (34) of the semiconductor body portion, a drain electrode (24) is formed on the top of the mesa, and a pair of gate electrode stripes (26) are formed on the active layer adjacent both sides of the mesa. When voltage (V.sub.G), negative with respect to the drain, is applied to the gate electrodes, the depletion regions (28) thereunder extend laterally in the active layer until they intersect, thereby pinching off the flow of current in the channel extending from the drain and source electrodes.
    Type: Grant
    Filed: July 5, 1979
    Date of Patent: November 25, 1980
    Assignee: Bell Telephone Laboratories, Incorporated
    Inventors: Alfred Y. Cho, James V. DiLorenzo
  • Patent number: 4231050
    Abstract: Surface recombination current in GaAs devices is reduced by means of a semi-insulating, oxygen, iron or chromium doped monocrystalline layer of AlGaAs grown by MBE. The AlGaAs layer is grown on a GaAs body and is then masked. Diffusion of suitable impurities through a window in the mask converts the exposed portions of the AlGaAs layer to low resistivity and modifies the conductivity of the underlying zone of the GaAs body. The peripheral portions of the AlGaAs layer, however, remain semi-insulating and are effective to reduce the surface recombination velocity - diffusion length product by more than an order of magnitude.
    Type: Grant
    Filed: January 30, 1979
    Date of Patent: October 28, 1980
    Assignee: Bell Telephone Laboratories, Incorporated
    Inventors: Horace C. Casey, Jr., Alfred Y. Cho, Philip W. Foy
  • Patent number: 4201998
    Abstract: A Schottky barrier semiconductor device and process for making same is described wherein edge breakdown is avoided by making the rectifying contact in a curved depression in an epitaxial active layer having a nonuniform doping profile. The depression is formed by anodizing a portion of the epitaxial layer and etching the anodic oxide. Etching and electroplating of the contact are done in the same solution to avoid contamination of the metal-semiconductor interface.
    Type: Grant
    Filed: May 30, 1978
    Date of Patent: May 6, 1980
    Assignee: Bell Telephone Laboratories, Incorporated
    Inventors: Alfred Y. Cho, Martin V. Schneider
  • Patent number: 4186410
    Abstract: A nonalloyed ohmic contact (110-112, 120-122) to an n-type Group III(a)-V(a) compound semiconductor body (102-104) is formed by epitaxially growing a Group III(a)-V(a) n.sup.++ -layer (106-108, 106'-108') doped to at least 10.sup.19 cm.sup.-3 between the semiconductor body and a metal contact layer (110-112). The metal layer forms an ohmic contact without requiring heating above the eutectic temperature. In order to avoid contamination of the metal-semiconductor interface, a metal contact layer (120-122) may be deposited in situ after MBE growth of the n.sup.++ -layer. This technique results in both a metal-semiconductor interface with smoother morphology and also an ohmic contact without heating above the eutectic temperature. These procedures are specifically described with reference to the fabrication of GaAs FETs.
    Type: Grant
    Filed: June 27, 1978
    Date of Patent: January 29, 1980
    Assignee: Bell Telephone Laboratories, Incorporated
    Inventors: Alfred Y. Cho, James V. Di Lorenzo, William C. Niehaus
  • Patent number: 4181544
    Abstract: Apparatus for molecular beam deposition sequentially on a plurality of substrates is described. The apparatus includes a growth chamber and an auxiliary (sample-exchange) chamber coupled by an air-lock. The substrates are carried by a rod which can be translated via a bellows mechanism between the two chambers. The auxiliary chamber includes a port which permits access to the samples so that the entire rod-bellows mechanism need not be removed in order to change samples. The auxiliary chamber also includes means for maintaining therein an inert atmosphere at a pressure in excess of atmospheric pressure especially when the port is open. The growth chamber includes a cylindrical liquid nitrogen (LN.sub.2) shroud which has an aperture in its wall to admit molecular beams to only a heated (growth) substrate. The unheated (idle) substrates are thus shaded from the beams. In addition, the shroud surrounds both the growth substrate and idle substrates in the growth chamber.
    Type: Grant
    Filed: October 30, 1978
    Date of Patent: January 1, 1980
    Assignee: Bell Telephone Laboratories, Incorporated
    Inventor: Alfred Y. Cho
  • Patent number: 4160261
    Abstract: In a metal-insulator-semiconductor (MIS) structure, the I-layer comprises a single-crystal, semi-insulating layer which forms a substantially lattice-matched heterojunction with the underlying S-layer. Illustratively, the structure, grown by MBE, includes an indirect gap AlGaAs I-layer doped with a deep level impurity such as oxygen, iron or chromium, and a GaAs S-layer. GaAs FETs incorporating this MIS structure are described.
    Type: Grant
    Filed: January 13, 1978
    Date of Patent: July 3, 1979
    Assignee: Bell Telephone Laboratories, Incorporated
    Inventors: Horace C. Casey, Jr., Alfred Y. Cho, Edward H. Nicollian
  • Patent number: 4137865
    Abstract: Apparatus for molecular beam deposition sequentially on a plurality of substrates is described. The apparatus includes a growth chamber and an auxiliary (sample-exchange) chamber coupled by an air-lock. The substrates are carried by a rod which can be translated via a bellows mechanism between the two chambers. The auxiliary chamber includes a port which permits access to the samples so that the entire rod-bellows mechanism need not be removed in order to change samples. The auxiliary chamber also includes means for maintaining therein an inert atmosphere at a pressure in excess of atmospheric pressure especially when the port is open. The growth chamber includes a cylindrical LN.sub.2 shroud which has an aperture in its wall to admit molecular beams to only a heated (growth) substrate. The unheated (idle) substrates are thus shaded from the beams. In addition, the shroud surrounds both the growth substrate and idle substrates in the growth chamber.
    Type: Grant
    Filed: December 30, 1976
    Date of Patent: February 6, 1979
    Assignee: Bell Telephone Laboratories, Incorporated
    Inventor: Alfred Y. Cho