Patents by Inventor Alfredo Cueva Gonzalez

Alfredo Cueva Gonzalez has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9955605
    Abstract: Techniques and mechanisms for providing connectivity to an integrated circuit device via a hardware interface. In an embodiment, the hardware interface includes contacts forming an array of nodes. Some or all such nodes are arranged in cells, wherein the respective node types of each cell's nodes are according to the same cell pattern. The cell pattern includes eight B nodes for the exchange of data bits, four strobe S nodes for the exchange of strobe signals, and ground (G) nodes for the providing of one or more reference potentials. The cell pattern enables formation of a lattice structure including node-contiguous G nodes each of a respective one of the multiple cells. In another embodiment, a ratio of bi-level nodes (including all S nodes and all G nodes) of the cell pattern to a total number of G nodes of the cell pattern is 12:8 or more.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: April 24, 2018
    Assignee: INTEL CORPORATION
    Inventors: Raul Enriquez Shibayama, Karen Navarro Castillo, Casey G Thielen, Alfredo Cueva Gonzalez, Benjamin Lopez Garcia
  • Publication number: 20170288327
    Abstract: Techniques and mechanisms for providing connectivity to an integrated circuit device via a hardware interface. In an embodiment, the hardware interface includes contacts forming an array of nodes. Some or all such nodes are arranged in cells, wherein the respective node types of each cell's nodes are according to the same cell pattern. The cell pattern includes eight B nodes for the exchange of data bits, four strobe S nodes for the exchange of strobe signals, and ground (G) nodes for the providing of one or more reference potentials. The cell pattern enables formation of a lattice structure including node-contiguous G nodes each of a respective one of the multiple cells. In another embodiment, a ratio of bi-level nodes (including all S nodes and all G nodes) of the cell pattern to a total number of G nodes of the cell pattern is 12:8 or more.
    Type: Application
    Filed: March 30, 2016
    Publication date: October 5, 2017
    Inventors: Raul Enriquez Shibayama, Karen Navarro Castillo, Casey G. Thielen, Alfredo Cueva Gonzalez, Benjamin Lopez Garcia
  • Publication number: 20170179369
    Abstract: A system and method of communicating among electronic devices on a platform. The method includes inducing, at a first device coupled to a substrate, mechanical vibrations in the substrate. Then the method further includes receiving the mechanical vibrations through the substrate at a second device coupled to the substrate. The mechanical vibrations are interpreted as a command to the second device. The second device acts on the command.
    Type: Application
    Filed: December 18, 2015
    Publication date: June 22, 2017
    Inventors: Sergio GARCIA DE ALBA GARCIN, Hector A. CORDOURIER MARURI, Alfredo CUEVA GONZALEZ, Jesus H. ALVAREZ MONROY, Juan F. RAMIREZ AGUILAR
  • Patent number: 9304561
    Abstract: The present disclosure is generally related to power management in a circuit on a circuit board of a processor. The circuit includes a first power connector coupled to a first power input rail. The circuit includes a second power connector and a second power input rail. The circuit includes a control module. The control module is configured to determine a power specification of the circuit board. The control module is configured to detect a power cable connected to the first control connector. The control module is configured to sense a voltage at the second power connector. The control module is configured to couple the second power input rail with the first power connector or the second power connector in response to the determined power specification of the circuit board and the sensed voltage at the second power connector.
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: April 5, 2016
    Assignee: Intel Corporation
    Inventors: Alfredo Cueva Gonzalez, Miguel Cervantes Lopez, Arturo Sanchez Hernandez, Georges Faure Vaquero, Richard Stamey, Jeffrey Colwell, Gautam Nath, Juan Ramirez Aguilar
  • Publication number: 20150067376
    Abstract: The present disclosure is generally related to power management in a circuit on a circuit board of a processor. The circuit includes a first power connector coupled to a first power input rail. The circuit includes a second power connector and a second power input rail. The circuit includes a control module. The control module is configured to determine a power specification of the circuit board. The control module is configured to detect a power cable connected to the first control connector. The control module is configured to sense a voltage at the second power connector. The control module is configured to couple the second power input rail with the first power connector or the second power connector in response to the determined power specification of the circuit board and the sensed voltage at the second power connector.
    Type: Application
    Filed: August 30, 2013
    Publication date: March 5, 2015
    Inventors: Alfredo Cueva Gonzalez, Miguel Cervantes Lopez, Arturo Sanchez Hernandez, Georges Faure Vaquero, Richard Stamey, Jeffrey Colwell, Gautam Nath, Robert Fite, Juan Ramirez Aguilar