Abstract: Integrated circuits may have programmable logic circuitry and hard-coded circuitry. The hard-coded circuitry may include data circuitry, a processor, and memory. As the hard-coded circuitry has a limited capacity, a portion of the programmable logic circuitry may be configured using configuration data to serve as expanded soft-coded memory for the hard-coded processor. Instructions for controlling settings of the data circuitry may be stored on the hard-coded and soft-coded memory. An additional portion of the programmable logic circuitry may be configured using the configuration data to serve as a soft-coded processor that executes the instructions stored on the soft-coded memory. Use of the soft-coded processor and/or expanded soft-coded memory may allow for more advanced algorithms for initialization and calibration of the data circuitry than when only hard-coded memory is used and may allow for updated processor circuitry to be implemented.

Abstract: Integrated circuits may have programmable logic circuitry and hard-coded circuitry. The hard-coded circuitry may include data circuitry, a processor, and memory. As the hard-coded circuitry has a limited capacity, a portion of the programmable logic circuitry may be configured using configuration data to serve as expanded soft-coded memory for the hard-coded processor. Instructions for controlling settings of the data circuitry may be stored on the hard-coded and soft-coded memory. An additional portion of the programmable logic circuitry may be configured using the configuration data to serve as a soft-coded processor that executes the instructions stored on the soft-coded memory. Use of the soft-coded processor and/or expanded soft-coded memory may allow for more advanced algorithms for initialization and calibration of the data circuitry than when only hard-coded memory is used and may allow for updated processor circuitry to be implemented.

Abstract: One embodiment relates to a method for compressing a data-stream of configuration data for electronically configuring an electronically-programmable semiconductor device having a two-dimensional (2D) block structure for an array of core resources. Inter-block and intra-block transformations may be applied to the data-stream to obtain a 2D-transformed data-stream which can be shorter and/or more compressible than the original data. Subsequently, one-dimensional (1D) compression that considers the configuration data as a sequence of bits (and does not consider the 2D block structure) may be applied to obtain a final compressed data sequence that is streamed to the electronically-programmable semiconductor device. Another embodiment relates to a method of decompressing the compressed data-stream of configuration data that is received by the semiconductor device. Other embodiments, aspects, and features are also disclosed.

Abstract: A block data compression system comprising a Compression unit and a Decompression unit, and an Algorithm for fast block data compression using multi-byte search. Objective of the invention is to develop a block data compression system and algorithm for fast block data compression with multi-byte search for optimal encoding during the learning phase of substitutional methods, allowing length-limited and relative small blocks of input data symbols to be compressed independently, as required by random-access storage or telecommunication devices; and reaching high-performance characteristics by employed accelerating architectures and highly pipelines data-flow principles.

Abstract: A block data compression system comprising a Compression unit and a Decompression unit, and an Algorithm for fast block data compression using multi-byte search. Objective of the invention is to develop a block data compression system and algorithm for fast block data compression with multi-byte search for optimal encoding during the learning phase of substitutional methods, allowing length-limited and relative small blocks of input data symbols to be compressed independently, as required by random-access storage or telecommunication devices; and reaching high-performance characteristics by employed accelerating architectures and highly pipelines data-flow principles.