Patents by Inventor Alfredo Ochoa

Alfredo Ochoa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230276946
    Abstract: A piece of ergonomic height-adjustable erotic furniture, having the general appearance of a normal divan, but capable of providing comfortable support for a number of different sexual positions for different heights, body types and health conditions of the participants, improving the quality and variety of their sexual interactions. The furniture has a board made with foam and covered in upholstery, designed to support the bodies of the participants, with inward concave edges and a front convex edge, a header raised with respect to this board, and adjustable height that raises and lowers the board parallel to the floor to facilitate a variety of sexual positions.
    Type: Application
    Filed: March 1, 2023
    Publication date: September 7, 2023
    Inventor: LUIS ALFREDO OCHOA NACAD
  • Patent number: 7817389
    Abstract: A semiconductor device for coupling a transient voltage at an input node to a reference node, the device having a bipolar transistor adapted to couple its collector to an input node and its emitter to the reference node and a driver device adapted to be coupled between the input node and the base terminal of the transistor such that the driver device is responsive to a transient voltage at the input node to turn on the transistor, thereby shunting the transient voltage to the reference node. Preferably, the input node is coupled to a high speed data transmission line that operates below 5 v and the reference node is coupled to ground and the transistor is an NPN transistor. The driver may preferably be a gate-drain connected MOS transistor with its gate-drain terminal coupled to the collector terminal of the transistor and its source terminal coupled to the base terminal of the transistor.
    Type: Grant
    Filed: February 18, 2009
    Date of Patent: October 19, 2010
    Inventors: Alfredo Ochoa, George Templeton, James Washburn
  • Publication number: 20090251833
    Abstract: A semiconductor device for coupling a transient voltage at an input node to a reference node, the device having a bipolar transistor adapted to couple its collector to an input node and its emitter to the reference node and a driver device adapted to be coupled between the input node and the base terminal of the transistor such that the driver device is responsive to a transient voltage at the input node to turn on the transistor, thereby shunting the transient voltage to the reference node. Preferably, the input node is coupled to a high speed data transmission line that operates below 5 v and the reference node is coupled to ground and the transistor is an NPN transistor. The driver may preferably be a gate-drain connected MOS transistor with its gate-drain terminal coupled to the collector terminal of the transistor and its source terminal coupled to the base terminal of the transistor.
    Type: Application
    Filed: February 18, 2009
    Publication date: October 8, 2009
    Inventors: Alfredo Ochoa, George Templeton, James Washburn
  • Publication number: 20060082938
    Abstract: A semiconductor device for coupling a transient voltage at an input node to a reference node, the device having a bipolar transistor adapted to couple its collector to an input node and its emitter to the reference node and a driver device adapted to be coupled between the input node and the base terminal of the transistor such that the driver device is responsive to a transient voltage at the input node to turn on the transistor, thereby shunting the transient voltage to the reference node. Preferably, the input node is coupled to a high speed data transmission line that operates below 5v and the reference node is coupled to ground and the transistor is an NPN transistor. The driver may preferably be a gate-drain connected MOS transistor with its gate-drain terminal coupled to the collector terminal of the transistor and its source terminal coupled to the base terminal of the transistor.
    Type: Application
    Filed: March 9, 2005
    Publication date: April 20, 2006
    Inventors: Alfredo Ochoa, George Templeton, James Washburn
  • Patent number: 6392266
    Abstract: A method is provided for suppressing a transient signal (VTR) using a single semiconductor die (130). The method comprises the step of loading the transient signal with first and second junctions (110, 112) formed adjacent to a first doped region (140) of the semiconductor die. The first junction breaks down to generate a current while the second junction forward biases to route the current across an undepleted portion (161) of the first doped region and through the second junction.
    Type: Grant
    Filed: January 25, 2001
    Date of Patent: May 21, 2002
    Assignee: Semiconductor Components Industries LLC
    Inventors: Francine Y. Robb, William E. Gandy, Jr., Alfredo Ochoa, Jeffrey Pearse