Abstract: When errors arise in a computing system that has plural modules, this invention corrects those errors. In the first instance, the invention excludes the computing system itself, but receives error messages from the plural modules of that system—along plural receiving connections, respectively. Plural sending connections return corrective responses to plural modules of that system, respectively. In a second instance, the invention further incorporates that system. The invention is hierarchical: plural levels or tiers of apparatus and function are present—a first (typically uppermost) one directly serving that system as described above, and others (lower) that analogously serve the first tier of the invention—and than also the subsequent tiers, in a cascading or nested fashion, down to preferably a bottom-level tier supporting all the upper ones. Each level preferably controls power interruption and restoration to higher levels. Ideally the hierarchy is in the form of a “system on chip”.

Abstract: ASICs or like fabrication-preprogrammed hardware provide controlled power and recovery signals to a computing system that is made up of commercial, off-the-shelf components—and that has its own conventional hardware and software fault-protection systems, but these are vulnerable to failure due to external and internal events, bugs, human malice and operator error. The computing system preferably includes processors and programming that are diverse in design and source. The hardware infrastructure uses triple modular redundancy to test itself as well as the computing system, and to remove failed elements—powering up and loading data into spares. The hardware is very simplified in design and programs, so that bugs can be thoroughly rooted out. Communications between the protected system and the hardware are protected by very simple circuits with duplex redundancy.

Abstract: When errors arise in a computing system that has plural modules, this invention corrects those errors. In the first instance, the invention excludes the computing system itself, but receives error messages from the plural modules of that system—along plural receiving connections, respectively. Plural sending connections return corrective responses to plural modules of that system, respectively. In a second instance, the invention further incorporates that system. The invention is hierarchical: plural levels or tiers of apparatus and function are present—a first (typically uppermost) one directly serving that system as described above, and others (lower) that analogously serve the first tier of the invention—and then also the subsequent tiers, in a cascading or nested fashion, down to preferably a bottom-level tier supporting all the upper ones. Each level preferably controls power interruption and restoration to higher levels. Ideally the hierarchy is in the form of a “system on chip”.

Abstract: ASICs or like fabrication-preprogrammed hardware provide controlled power and recovery signals to a computing system that is made up of commercial, off-the-shelf components—and that has its own conventional hardware and software fault-protection systems, but these are vulnerable to failure due to external and internal events, bugs, human malice and operator error. The computing system preferably includes processors and programming that are diverse in design and source. The hardware infrastructure uses triple modular redundancy to test itself as well as the computing system, and to remove failed elements—powering up and loading data into spares. The hardware is very simplified in design and programs, so that bugs can be thoroughly rooted out. Communications between the protected system and the hardware are protected by very simple circuits with duplex redundancy.

Abstract: When errors arise in a computing system that has plural modules, this invention corrects those errors. In the first instance, the invention excludes the computing system itself, but receives error messages from the plural modules of that system—along plural receiving connections, respectively. Plural sending connections return corrective responses to plural modules of that system, respectively. In a second instance, the invention further incorporates that system. The invention is hierarchical: plural levels or tiers of apparatus and function are present—a first (typically uppermost) one directly serving that system as described above, and others (lower) that analogously serve the first tier of the invention—and then also the subsequent tiers, in a cascading or nested fashion, down to preferably a bottom-level tier supporting all the upper ones. Each level preferably controls power interruption and restoration to higher levels. Ideally the hierarchy is in the form of a “system on chip”.

Abstract: ASICs or like fabrication-preprogrammed hardware provide controlled power and recovery signals to a computing system that is made up of commercial, off-the-shelf components—and that has its own conventional hardware and software fault-protection systems, but these are vulnerable to failure due to external and internal events, bugs, human malice and operator error. The computing system preferably includes processors and programming that are diverse in design and source. The hardware infrastructure uses triple modular redundancy to test itself as well as the computing system, and to remove failed elements—powering up and loading data into spares. The hardware is very simplified in design and programs, so that bugs can be thoroughly rooted out. Communications between the protected system and the hardware are protected by very simple circuits with duplex redundancy.