Abstract: A parallel operation linear feedback shift-register (LFSR) that generates random test patterns or creates a signature that represents the response of a device under test at ultra high speed using low speed components and/or a slow rate clock. The apparatus is comprised of: a register connected to an external clock, and a plurality of combinatorial logic networks sequentially connected, the last of which drives the register which in turn feeds back into the first of the combinatorial logic networks. Each of the combinatorial networks provides a pseudo-random pattern which are then outputted in parallel, thereby creating a high speed data flow. By providing additional data inputs to the combinatorial networks, the pseudo-random patterns become the signature of the input data.

Abstract: A method, and apparatus for accomplishing the method, for controlling an operation of a test pin of a per-pin semiconductor device test system. The method includes the steps of, during a test cycle, generating a plurality of timing signals, providing a test pattern comprised of M-bits, and decoding the M-bits into one of 2.sup.M first multi-bit control words. In accordance with logical states of bits of the first control word, the method selects specified ones of the timing signals and generates a stimulus signal at a test pin in accordance with the selected specified ones of the timing signals. In accordance with an aspect of the invention, the step of providing provides test patterns at a rate of (x) test patterns per second, the step of generating generates test pin stimulus signals at a rate of (y) stimulus signals per second, and wherein (y)=n(x), where (n) is an integer greater than one.

Abstract: A programmable pulse generator that uses high resolution programmable delay circuits (HRPDCs) as building blocks, each of which is capable of changing timing "on-the-fly", i.e., modifying the programmable delay within one tester cycle and without the limitations of existing delay circuits. The pulse generator comprises a timing control array that is subdivided into three components providing coarse delay, fine delay and extra-fine delay; a plurality of timing generators respectively controlled by the timing control array, each generator further comprising a plurality of HRPDCs, programmable delay circuits, and fixed delay blocks appropriately combined to modify pulse delay and pulse edges within each cycle.

Abstract: An Algorithmic Test Pattern Generator (APG) of sufficient simplicity to be replicated at every pin of a tester. This APG is comprised of two counters and various controls capable of manipulating the counters and generating output data which is based on command and counter status. The circuit is capable of testing VLSI logic and analog circuitry, and is specifically well suited to test embedded arrays that can only be accessed through LSSD shift register chains.

Abstract: Apparatus and method for controlling an operation of a test pin of a per-pin semiconductor device test system [10]. The apparatus includes pattern storage memory [42] for storing and for outputting information related to a state of the test pin for individual ones of a plurality of consecutive test cycles, pattern processor [14] having an input coupled to the pattern storage memory for generating for each of the test cycles words comprised of M bits, and a test pin control memory [18] having an input coupled to the output of the pattern processor for decoding each of the words into 2.sup.M or less command words. Each of the decoded command words includes a plurality of control bits. Predetermined ones of the plurality of control bits are coupled to pin driver electronics [24,28] for specifying, for each of the test cycles, at least one characteristic of an electrical signal transmitted to the test pin.

Abstract: A driver circuit is disclosed for use in testing bi-directional transceiver semiconductor products using a minimum of time and number of product accessing pins. The driver includes a pair of controllable amplitude current sources whose output currents are selectably switched into or partially away from the commonly connected emitters of a current switch. The current switch is energized by a variable voltage source and produces the output test voltage.

Abstract: Disclosed is a method and circuit for reducing and maintaining constant overshoot in a high speed driver. The circuit includes a predriver circuit which is driven single endedly and a driver circuit which is differentially driven by the predriver outputs. The predriver and the driver are differential pairs, with commonly controlled individual transistor current sources. A diode has been added in series with each emitter of the differential pairs. Schottky diodes are preferable because of their low capacitance. The diodes increase the input switching voltage (the smallest input voltage swing that will cause the outputs to fully switch) of the differential pair because they must also be switched on and off. The increase results in an increase in effective transition time, which results in smaller overshoots because the circuit is being switched slower. The output amplitude of the driver is set by a voltage which controls the current source currents of the commonly controlled current sources.

Abstract: An array testing apparatus includes a plurality of pin pattern generators for individually generating serial bit sequences required at each pin of a device under test during the testing operation. The individual pin pattern generators receive starting addresses from one or more programmable controllers and each pin pattern generator then performs a subroutine to repeat basic patterns or combinations of basic patterns as necessary. Both the pin pattern generators and the programmable controllers may include loop logic for obtaining the desired repetition sequences.

Abstract: A high-speed programmable timing generator in which a continuously cycling binary count is compared with an input data word. Predetermined bits, starting from the highest-order end of the counter, can be selectively inhibited to effectively vary the cycle period of the counter. The digital word with which the output of the counter is compared can be varied to set the reference phase of the output timing pulse stream. Further, fine delay adjustment of the phase of the output timing pulse stream is effected by a controllable phase-locked loop.

Abstract: In the method for fabricating a semiconductor substrate integrated circuit layout including: forming a plurality of spaced-apart circuit cells in columnar arrays within said substrate; forming a first insulating layer above said substrate, said layer having apertures therein to expose selected active regions of said selected cells; the improvement comprising: depositing first and second sets of elongated conductors in substantially parallel relationship atop said first insulating layer in said columnar direction; said first set being disposed directly atop said exposed cells to make selected contact with selected ones of said exposed active regions through said apertures in said first insulating layer; said second set being disposed in areas between said exposed cells; forming a second insulating layer above said first and second sets of conductors, said second insulating layer having apertures therein to expose selected ones of said first and second sets; and depositing a third set of substantially parallel,