Patents by Inventor Ali A. El-Moursy
Ali A. El-Moursy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9459918Abstract: Scheduling threads in a multi-threaded/multi-core processor having a given instruction window, and scheduling a predefined number N of threads among a set of M active threads in each context switch interval are provided. The actual power consumption of each running thread during a given context switch interval is determined, and a predefined priority level is associated with each thread among the active threads based on the actual power consumption determined for the threads. The power consumption expected for each active thread during the next context switch interval in the current instruction window (CIW_Power_Th) is predicted, and a set of threads to be scheduled among the active threads are selected from the priority level associated with each active thread and the power consumption predicted for each active thread in the current instruction window.Type: GrantFiled: January 30, 2014Date of Patent: October 4, 2016Assignee: International Business Machines CorporationInventors: Ali A. El-Moursy, Hisham E. Elshishiny, Ahmed T. Sayed Gamal El Din
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Publication number: 20140149990Abstract: Scheduling threads in a multi-threaded/multi-core processor having a given instruction window, and scheduling a predefined number N of threads among a set of M active threads in each context switch interval are provided. The actual power consumption of each running thread during a given context switch interval is determined, and a predefined priority level is associated with each thread among the active threads based on the actual power consumption determined for the threads. The power consumption expected for each active thread during the next context switch interval in the current instruction window (CIW_Power_Th) is predicted, and a set of threads to be scheduled among the active threads are selected from the priority level associated with each active thread and the power consumption predicted for each active thread in the current instruction window.Type: ApplicationFiled: January 30, 2014Publication date: May 29, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ali A. EL-MOURSY, Hisham E. ELSHISHINY, Ahmed T. SAYED GAMAL EL DIN
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Patent number: 8677361Abstract: Scheduling threads in a multi-threaded/multi-core processor having a given instruction window, and scheduling a predefined number N of threads among a set of M active threads in each context switch interval are provided. The actual power consumption of each running thread during a given context switch interval is determined, and a predefined priority level is associated with each thread among the active threads based on the actual power consumption determined for the threads. The power consumption expected for each active thread during the next context switch interval in the current instruction window (CIW_Power_Th) is predicted, and a set of threads to be scheduled among the active threads are selected from the priority level associated with each active thread and the power consumption predicted for each active thread in the current instruction window.Type: GrantFiled: September 28, 2011Date of Patent: March 18, 2014Assignee: International Business Machines CorporationInventors: Ali A. El-Moursy, Hisham E. Elshishiny, Ahmed T. Sayed Gamal El Din
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Patent number: 8640133Abstract: Fetch operations are assigned to different threads in a multithreaded environment. There are provided a number of different sorting algorithms, from which one is periodically selected on the basis of whether the present algorithm is giving satisfactory results or not. The period is preferably a sub-context interval. The different sorting algorithms preferably include a software/OS priority. A second sorting algorithm may include sorting according to hardware performance measurements. Two-level priority scheme is used to combine both priorities. The judgement of satisfactory performance is preferably based on the difference between a desired number of fetch operations attributed per sub-context switch interval to each thread and a real number of fetch operations attributed per sub-context switch interval to each thread.Type: GrantFiled: December 18, 2009Date of Patent: January 28, 2014Assignee: International Business Machines CorporationInventors: Hisham El-Shishiny, Ali El-Moursy
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Patent number: 8356304Abstract: Logical processors/hardware contexts are assigned to different jobs/threads in a multithreaded/multicore environment. There are provided a number of different sorting algorithms, from which one is periodically selected on the basis of whether the present algorithm is giving satisfactory results or not. The period is preferably a super-context interval. The different sorting algorithms preferably include a software/OS priority. A second sorting algorithm may include sorting according to hardware performance measurements. The judgement of satisfactory performance is preferably based on the difference between a desired number of time quantum attributed per super-context switch interval to each job/thread and a real number of time quantum attributed per super-context switch interval to each job/thread.Type: GrantFiled: June 30, 2010Date of Patent: January 15, 2013Assignee: International Business Machines CorporationInventors: Ali El-Moursy, Hisham El-Shishiny
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Publication number: 20120192195Abstract: Scheduling threads in a multi-threaded/multi-core processor having a given instruction window, and scheduling a predefined number N of threads among a set of M active threads in each context switch interval are provided. The actual power consumption of each running thread during a given context switch interval is determined, and a predefined priority level is associated with each thread among the active threads based on the actual power consumption determined for the threads. The power consumption expected for each active thread during the next context switch interval in the current instruction window (CIW_Power_Th) is predicted, and a set of threads to be scheduled among the active threads are selected from the priority level associated with each active thread and the power consumption predicted for each active thread in the current instruction window.Type: ApplicationFiled: September 28, 2011Publication date: July 26, 2012Applicant: International Business Machines CorporationInventors: Ali A. El-Moursy, Hisham E. Elshishiny, Ahmed T. Sayed Gamal El Din
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Patent number: 7979672Abstract: A method and system for transposing a multi-dimensional array for a multi-processor system having a main memory for storing the multi-dimensional array and a local memory is provided. One implementation involves partitioning the multi-dimensional array into a number of equally sized portions in the local memory, in each processor performing a transpose function including a logical transpose on one of said portions and then a physical transpose of said portion, and combining the transposed portions and storing back in their original place in the main memory.Type: GrantFiled: July 25, 2008Date of Patent: July 12, 2011Assignee: International Business Machines CorporationInventors: Ahmed H. M. R. El-Mahdy, Ali A. El-Moursy, Hisham ElShishiny
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Publication number: 20110004883Abstract: Logical processors/hardware contexts are assigned to different jobs/threads in a multithreaded/multicore environment. There are provided a number of different sorting algorithms, from which one is periodically selected on the basis of whether the present algorithm is giving satisfactory results or not. The period is preferably a super-context interval. The different sorting algorithms preferably include a software/OS priority. A second sorting algorithm may include sorting according to hardware performance measurements. The judgement of satisfactory performance is preferably based on the difference between a desired number of time quantum attributed per super-context switch interval to each job/thread and a real number of time quantum attributed per super-context switch interval to each job/thread.Type: ApplicationFiled: June 30, 2010Publication date: January 6, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: ALI EL-MOURSY, HISHAM EL-SHISHINY
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Publication number: 20100162041Abstract: Fetch operations are assigned to different threads in a multithreaded environment. There are provided a number of different sorting algorithms, from which one is periodically selected on the basis of whether the present algorithm is giving satisfactory results or not. The period is preferably a sub-context interval. The different sorting algorithms preferably include a software/OS priority. A second sorting algorithm may include sorting according to hardware performance measurements. Two-level priority scheme is used to combine both priorities. The judgement of satisfactory performance is preferably based on the difference between a desired number of fetch operations attributed per sub-context switch interval to each thread and a real number of fetch operations attributed per sub-context switch interval to each thread.Type: ApplicationFiled: December 18, 2009Publication date: June 24, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Hisham El-Shishiny, Ali El-Moursy
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Publication number: 20100023728Abstract: A method and system for transposing a multi-dimensional array for a multi-processor system having a main memory for storing the multi-dimensional array and a local memory is provided. One implementation involves partitioning the multi-dimensional array into a number of equally sized portions in the local memory, in each processor performing a transpose function including a logical transpose on one of said portions and then a physical transpose of said portion, and combining the transposed portions and storing back in their original place in the main memory.Type: ApplicationFiled: July 25, 2008Publication date: January 28, 2010Applicant: International Business Machines CorporationInventors: Ahmed H.M.R. El-Mahdy, Ali A. El-Moursy, Hisham ElShishiny