Patents by Inventor Ali A. Iranmanesh
Ali A. Iranmanesh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 5387552Abstract: A pnp device in a BiCMOS structure (1). PNP transistors (4) are fabricated without the need for additional process steps on the same substrate as npn (2), PMOS (8), and NMOS (6) devices. The process not only requires a minimum number of additional process steps, but results in devices with near optimum device characteristics.Type: GrantFiled: September 14, 1992Date of Patent: February 7, 1995Assignee: National Semiconductor CorporationInventor: Ali A. Iranmanesh
-
Patent number: 5374566Abstract: A method of fabricating a bipolar transistor on a semiconductor wafer is provided. The method includes steps of implanting p-type dopants into diffusion compensation regions (23) where an intrinsic base region (18) intersects an isolation oxide (31). The implant step is carried out before depositing a poly layer (from which an emitter contact (27a) is formed). Thus, the diffusion compensation region (23) is also located below the emitter contact (27a). A diffused emitter (27b) is subsequent formed by diffusing dopant from the emitter contact (27a) into the underlying active area.Type: GrantFiled: January 27, 1993Date of Patent: December 20, 1994Assignee: National Semiconductor CorporationInventor: Ali Iranmanesh
-
Patent number: 5338694Abstract: A BiCMOS method and device. The BiCMOS device achieves improved performance through the use of wrap-around silicide contacts, improved MOS gate formation, the use of n- and p-type LDD's, the formation of very shallow base regions in bipolar transistors, and through separate implants for base regions of the bipolar transistors and source/drains of the MOSFETS.Type: GrantFiled: March 9, 1992Date of Patent: August 16, 1994Assignee: National Semiconductor CorporationInventors: Vida Ilderem, Ali A. Iranmanesh, Alan G. Solheim, Christopher S. Blair, Rick C. Jerome, Rajeeva Lahri, Madan Biswal
-
Patent number: 5338696Abstract: A BiCMOS method and device. The BiCMOS device achieves improved performance through the use of wraparound silicide contacts, improved MOS gate formation, the use of n- and p-type LDD's, the formation of very shallow base regions in bipolar transistors, and through separate implants for base regions of the bipolar transistors and source/drains of the MOSFETS.Type: GrantFiled: March 1, 1993Date of Patent: August 16, 1994Assignee: National Semiconductor CorporationInventors: Vida Ilderem, Ali A. Iranmanesh, Alan G. Solheim, Christopher S. Blair, Rick C. Jerome, Rajeeva Lahri, Madan Biswal
-
Patent number: 5302551Abstract: A method is provided for planarizing the surface of an integrated circuit over a metal interconnect layer. Metal interconnect lines and surrounding regions of a partially fabricated integrated circuit are first coated with a thin layer of dielectric substantially free of voids and then coated with a polysilicon layer. The polysilicon layer is planarized back to the level of the dielectric layer on top of the interconnects, providing a substantially planar surface for subsequent fabrication steps including deposition of a second dielectric layer and an overlying metal layer.Type: GrantFiled: May 11, 1992Date of Patent: April 12, 1994Assignee: National Semiconductor CorporationInventors: Ali Iranmanesh, John M. Pierce
-
Patent number: 5262672Abstract: A method and apparatus for reducing interconnection capacitance. A lightly doped buried layer is provided in or on a substrate below a field oxide region. The capacitance of an interconnect on the field oxide is significantly reduced by the lightly doped buried layer. When using a p-type substrate, the lightly doped buried layer may, for example, be a lightly doped (10.sup.13 /cm.sup.3) n-type region. Junction capacitance of, for example, a bipolar transistor is also reduced.Type: GrantFiled: November 27, 1991Date of Patent: November 16, 1993Assignee: National Semiconductor CorporationInventor: Ali A. Iranmanesh
-
Patent number: 5242854Abstract: A high performance bipolar transistor and a method of fabrication. Base resistance is reduced by a self-aligned silicide formed in the single-crystal region of the extrinsic base, thereby eliminating the polysilicon to single-crystal contact resistance as well as shunting the resistance of the single-crystal extrinsic base region. Oxide from the sidewall of the polysilicon local interconnection is selectively removed prior to silicide formation. Therefore, selected sidewalls of the poly interconnect layer also becomes silicided. This results in significant reductions in resistance of the interconnection, particularly for submicron geometries. Improved techniques for forming field oxide regions and for forming base regions of bipolar transistors are also disclosed.Type: GrantFiled: May 7, 1992Date of Patent: September 7, 1993Assignee: National Semiconductor CorporationInventors: Alan G. Solheim, Christopher S. Blair, Vida Ilderem, Ali A. Iranmanesh
-
Patent number: 5236863Abstract: A process for forming an IC isolation trench pattern wherein the trenches have varying widths and are filled with near intrinsic single crystal silicon. Thus, the wiring that passes over the trenches has low capacitance and active circuit devices having improved high frequency performance can be fabricated into the silicon in the trenches. This increases the utilization of surface area thereby increasing active device density for VLSI applications.Type: GrantFiled: June 1, 1992Date of Patent: August 17, 1993Assignee: National Semiconductor CorporationInventor: Ali Iranmanesh
-
Patent number: 5234847Abstract: A BiCMOS method and device. The BiCMOS device achieves improved performance through the use of silicide contacts overlying doped polysilicon which extend fully up to and contact sidewall oxide formations. Silicide contacts in emitter regions and gate regions are separated from silicide contacts of base contacts and source and drain contacts only by the thickness of the sidewall oxides, which are adjacent the emitter region and gate regions.Type: GrantFiled: November 6, 1991Date of Patent: August 10, 1993Assignee: National Semiconductor CorporationInventor: Ali A. Iranmanesh
-
Patent number: 5212102Abstract: An improved method for fabricating polysilicon Schottky clamped transistors and vertical fuse devices in the same semiconductor structure is disclosed. The resulting structure yields an improved Schottky clamped transistor and vertical fuse device. The improved Schottky transistor has a silicide rectifying contact between the base and collector of the transistor, the vertical fuse is provided with a direct contact between an aluminum contact metal and a polysilicon emitter contact.Type: GrantFiled: June 5, 1992Date of Patent: May 18, 1993Assignee: National Semiconductor CorporationInventors: Ali A. Iranmanesh, George E. Ganschow
-
Patent number: 5169794Abstract: A pnp device in BiCMOS structure (1). PNP transistors (4) are fabricated without the need for additional process steps on the same substrate as npn (2), PMOS (8), and NMOS (6) devices. The process not only requires a minimum number of additional process steps, but results in devices with near optimum device characteristics.Type: GrantFiled: March 22, 1991Date of Patent: December 8, 1992Assignee: National Semiconductor CorporationInventor: Ali A. Iranmanesh
-
Patent number: 5144404Abstract: An improved method for fabricating polysilicon Schottky clamped transistors and vertical fuse devices in the same semiconductor structure is disclosed. The resulting structure yields an improved Schottky clamped transistor and vertical fuse device. The improved Schottky transistor has a silicide rectifying contact between the base and collector of the transistor, the vertical fuse is provided with a direct contact between an aluminum contact metal and a polysilicon emitter contact.Type: GrantFiled: August 22, 1990Date of Patent: September 1, 1992Assignee: National Semiconductor CorporationInventors: Ali A. Iranmanesh, George E. Ganschow
-
Patent number: 5139961Abstract: A high performance bipolar transistor and a method of fabrication. Base resistance is reduced by a self-aligned silicide formed in the single-crystal region of the extrinsic base, thereby eliminating the polysilicon to single-crystal contact resistance as well as shunting the resistance of the single-crystal extrinsic base region. Oxide from the sidewall of the polysilicon local interconnection is selectively removed prior to silicide formation. Therefore, selected sidewalls of the poly interconnect layer also becomes silicided. This results in significant reductions in resistance of the interconnection, particularly for sub-micron geometries. Improved techniques for forming field oxide regions and for forming base regions of bipolar transistors are also disclosed.Type: GrantFiled: April 2, 1990Date of Patent: August 18, 1992Assignee: National Semiconductor CorporationInventors: Alan G. Solheim, Bamdad Bastani, James L. Bouknight, George E. Ganschow, Bancherd Delong, Rajeeva Lahri, Steve M. Leibiger, Christopher S. Blair, Rick C. Jerome, Madan Biswal, Tad Davies, Vida Ilderem, Ali A. Iranmanesh
-
Patent number: 5124775Abstract: A semiconductor device and method to reduce the size of bipolar transistors and decrease the number of steps required to fabricate the bipolar transistor by using a unitary contiguous oxide sidewall to separate a collector contact from the base, emitter and emitter contact. The device and method may also be used during the fabrication of BiCMOS devices.Type: GrantFiled: July 23, 1990Date of Patent: June 23, 1992Assignee: National Semiconductor CorporationInventor: Ali A. Iranmanesh
-
Patent number: 5107320Abstract: A method and apparatus for reducing interconnection capacitance. A lightly doped buried layer is provided in or on a substrate below a field oxide region. The capacitance of an interconnect on the field oxide is significantly reduced by the lightly doped buried layer. When using a p-type substrate, the lightly doped buried layer may, for example, be a lightly doped (10.sup.13 /cm.sup.3) n-type region. Junction capacitance of, for example, a bipolar transistor is also reduced.Type: GrantFiled: February 1, 1991Date of Patent: April 21, 1992Assignee: National Semiconductor CorporationInventor: Ali A. Iranmanesh
-
Patent number: 5059555Abstract: An improved method for fabricating polysilicon Schottky clamped transistors and vertical fuse devices in the same semiconductor structure is disclosed. The resulting structure yields an improved Schottky clamped transistor and vertical fuse device. The improved Schottky transistor has a silicide rectifying contact between the base and collector of the transistor, the vertical fuse is provided with a direct contact between an aluminum contact metal and a polysilicon emitter contact.Type: GrantFiled: August 20, 1990Date of Patent: October 22, 1991Assignee: National Semiconductor CorporationInventors: Ali A. Iranmanesh, Lawrence K. C. Lam
-
Patent number: 4933733Abstract: An improved semiconductor device is presented, the improvement comprising a slot collector contact region (38). The slot collector contact region (38) is formed in a semiconductor substrate (39) adjacent to base and emitter regions (40,44) of the bipolar semiconductor device. The slot collector contact region (38) is comprised of a slot filled with a filler material. In a preferred embodiment of the invention, the slot collector contact region (38) is separated from the base and emitter regions (40,44) by an insulating layer (52).Type: GrantFiled: November 12, 1986Date of Patent: June 12, 1990Assignee: Advanced Micro Devices, Inc.Inventors: Ali Iranmanesh, Christopher O. Schmidt
-
Patent number: 4829025Abstract: An improved process is described for patterning films or layers, for example, in the manufacture of integrated circuit structures including bipolar and MOS devices on a silicon substrate, without damaging areas of the underlying substrate material, e.g., those portions of the substrate wherein active elements of an integrated circuit components will be formed. The process comprises patterning films or layers of dissimilar materials which respond differently to etchants to form a portion of masking materials over a selected area of an underlying substrate material and subsequently removing these masking materials using wet etching, at those steps in the process when damage to the underlying substrate material by dry etching may occur, to avoid damage to the underlying material by dry etching.Type: GrantFiled: October 2, 1987Date of Patent: May 9, 1989Assignee: Advanced Micro Devices, Inc.Inventor: Ali Iranmanesh
-
Patent number: 4800171Abstract: An improved method is described for constructing one or more integrated circuit components including bipolar and MOS devices on a silicon substrate without damaging areas of the substrate wherein active elements of the integrated circuit components will be formed. The method comprises forming multilayer pedestals of masking materials over the active regions of the substrate and subsequently removing these masking materials using wet etching to avoid damage to the substrate by dry etching.Type: GrantFiled: October 2, 1987Date of Patent: January 24, 1989Assignee: Advanced Micro Devices, Inc.Inventors: Ali Iranmanesh, Mammen Thomas
-
Patent number: 4745087Abstract: An improved method of making a bipolar transistor is disclosed which comprises forming one or more mask layers over a silicon substrate, etching at least one of said one or more masking layers to define a base contact area and a spaced apart collector contact area with an unetched emitter contact area defined in-between, forming a collector slot in a substrate of an integrated circuit structure through the collector contact area defined in the one or more mask layers, oxidizing the sidewall of the collector slot, filling the collector slot and the base and collector contact regions with polysilicon, removing one or more of the mask layers between the polysilicon base and collector contacts, oxidizing the exposed sidewalls of the polysilicon base and collector contacts, forming an emitter contact region between said collector and base contact regions insulated from the base and collector contacts by the sidewall oxidation thereon, and forming a base region in said substrate spaced from the collector slot by thType: GrantFiled: January 13, 1987Date of Patent: May 17, 1988Assignee: Advanced Micro Devices, Inc.Inventor: Ali Iranmanesh