Patents by Inventor Ali Akbar Sohanghpurwala

Ali Akbar Sohanghpurwala has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11531773
    Abstract: An apparatus, method, and system assess the trustworthiness of a design representation while maintaining its confidentiality and thwarting attempts at unauthorized access, misappropriation, and reverse engineering of confidential proprietary aspects of the design representation and/or its bit stream. A utility/tool is provided for trust assessment and verification of designs and/or bit streams. The utility/tool may be instantiated on a semiconductor device or implemented as a utility executable on a mobile computing device or other information processing system, apparatus, or network.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: December 20, 2022
    Assignee: GRAF RESEARCH CORPORATION
    Inventors: Jonathan Peter Graf, Ali Asgar Ali Akbar Sohanghpurwala, Scott Jeffery Harper
  • Publication number: 20210117556
    Abstract: An apparatus, method, and system assess the trustworthiness of a design representation while maintaining its confidentiality and thwarting attempts at unauthorized access, misappropriation, and reverse engineering of confidential proprietary aspects of the design representation and/or its bit stream. A utility/tool is provided for trust assessment and verification of designs and/or bit streams. The utility/tool may be instantiated on a semiconductor device or implemented as a utility executable on a mobile computing device or other information processing system, apparatus, or network.
    Type: Application
    Filed: December 28, 2020
    Publication date: April 22, 2021
    Inventors: Jonathan Peter GRAF, Ali Asgar Ali Akbar SOHANGHPURWALA, Scott Jeffery HARPER
  • Patent number: 10902132
    Abstract: An apparatus, method and system are disclosed which may be used for assessing the trustworthiness of a particular proprietary microelectronics device design representation in a manner that will maintain its confidentiality and, among other things, thwart attempts at unauthorized access, misappropriation and reverse engineering of the confidential proprietary aspects contained in the design representation and/or its bit stream design implementation format. The disclosed method includes performing a process for assessing/verifying a particular microelectronics device design representation and then providing some indication of the trustworthiness of that representation. An example utility/tool which implements the disclosed method is described that is particularly useful for trust assessment and verification of FPGA designs.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: January 26, 2021
    Assignee: Graf Research Corporation
    Inventors: Jonathan Peter Graf, Ali Asgar Ali Akbar Sohanghpurwala, Scott Jeffery Harper
  • Publication number: 20190065757
    Abstract: An apparatus, method and system are disclosed which may be used for assessing the trustworthiness of a particular proprietary microelectronics device design representation in a manner that will maintain its confidentiality and, among other things, thwart attempts at unauthorized access, misappropriation and reverse engineering of the confidential proprietary aspects contained in the design representation and/or its bit stream design implementation format. The disclosed method includes performing a process for assessing/verifying a particular microelectronics device design representation and then providing some indication of the trustworthiness of that representation. An example utility/tool which implements the disclosed method is described that is particularly useful for trust assessment and verification of FPGA designs.
    Type: Application
    Filed: August 25, 2017
    Publication date: February 28, 2019
    Inventors: Jonathan Peter GRAF, Ali Asgar Ali Akbar SOHANGHPURWALA, Scott Jeffery HARPER
  • Patent number: 5964992
    Abstract: A graphite reference electrode for use in the cathodic protection of steel embedded in concrete has been produced with a stable catalyzed structure that when equilibrated with air or oxygen and an electrolyte reaches a reproducible and reversible redox potential. This stable device is produced by exposure to hydrogen peroxide, impregnating with a metal oxide followed by a coating treatment. The embedded catalyzed graphite reference electrodes can be used in impressed cathodic protection systems or monitoring the corrosion condition of embedded steel to provide an early warning of impending damage.
    Type: Grant
    Filed: July 20, 1998
    Date of Patent: October 12, 1999
    Assignee: Giner, Inc.
    Inventors: Larry L. Swette, Mourad Manoukian, Monjid Hamdan, Anthony LaConti, Ali Akbar Sohanghpurwala, William T. Scannell